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This document was watermarked on 27-04-2011 at 16:37:42 local time.
Silicon Image
Confidential
for
PEARMAIN Electronics
Internal Use Only
Data Sheet
SiI9013 HDMI Receiver
Data Sheet
Document # SiI-DS-0232-D01
Silicon Image
Confidential
for
PEARMAIN Electronics
Internal Use Only
SiI9013 HDMI Receiver
Data Sheet
Silicon Image, Inc.
ii © 2008-2010 Silicon Image, Inc. All rights reserved. SiI-DS-0232-D01
CONFIDENTIAL
June 2010
Copyright Notice
Co
pyright © 2008-2010 Silicon Image, Inc. All rights reserved. These materials contain proprietary and confidential
information (including trade secrets, copyright and other interests) of Silicon Image, Inc. You may not use these
materials except only for your bona fide non-commercial evaluation of your potential purchase of products and/or
services from Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services
from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to
copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise
make these materials available, in whole or in part, to any third party.
Patents
The s
ubject matter described herein contains one or more inventions claimed in patents and/or patents pending owned by
Silicon Image, Inc., including but not limited to the inventions claimed in US patents #6,914,637, #6,151,334,
#6,026,124, #5,974,464 and #5,825,824.
Trademark Acknowledgment
Silico
n Image™, VastLane™, SteelVine™, PinnaClear™, Simplay™, Simplay HD™, Satalink™, and TMDS™ are
trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. HDMI
®
, the HDMI
logo and High-Definition Multimedia Interface™ are trademarks or registered trademarks of, and are used under license
from, HDMI Licensing, LLC.
Export Controlled Document
Thi
s document contains information subject to the Export Administration Regulations (EAR) and has a classification of
EAR99 or is controlled for Anti-Terrorism (AT) purposes. Transfer of this information by any means to an EAR Country
Group E:1 or foreign national thereof (whether in the U.S. or abroad) may require an export license or other approval from
the U.S. Department of Commerce. For more information, contact the Silicon Image Director of Global Trade Compliance.
Further Information
To
request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit
the Silicon Image, Inc. web site at www.siliconimage.com
.
Revision History
Revision Date Comment
A 12/2006 First Production release
B 12/2006 Updated packaging information
C 8/2007 Updated template and packaging information
D 7/2008 Updated S/PDIF Frequency support and MCLK properties
D01 6/2010 Updated page 1 and layout to prepare Data Brief; minor editing throughout.
© 2008-2010 Silicon Image. Inc. All rights reserved.
Silicon Image
Confidential
for
PEARMAIN Electronics
Internal Use Only
SiI9013 HDMI Receiver
Data Sheet
Silicon Image, Inc.
SiI-DS-0232-D01 © 2008-2010 Silicon Image, Inc. All rights reserved. iii
CONFIDENTIAL
Table of Contents
General Description .............................................................................................................................................................. 1
Digital Video Interface ..................................................................................................................................................... 1
Digital Audio Interface ..................................................................................................................................................... 1
HDCP ............................................................................................................................................................................... 1
Package ............................................................................................................................................................................. 1
Comparison of the SiI9013 with SiI9993 and SiI9025 receivers ...................................................................................... 2
Pin Diagram ...................................................................................................................................................................... 3
System Applications ............................................................................................................................................................. 4
Functional Description ......................................................................................................................................................... 4
TMDS Digital Core .......................................................................................................................................................... 4
Active Port Detection ................................................................................................................................................... 4
HDCP Decryption Engine/XOR Mask ............................................................................................................................. 4
HDCP Keys .................................................................................................................................................................. 5
HDCP BIST .................................................................................................................................................................. 6
Data Input and Conversion ............................................................................................................................................... 6
Mode Control Logic ..................................................................................................................................................... 6
Video Data Conversion and Video Output ................................................................................................................... 6
Automatic Video Configuration ................................................................................................................................... 8
Audio Processing Logic ................................................................................................................................................ 9
Auto Audio Configuration ............................................................................................................................................ 9
Soft Mute ...................................................................................................................................................................... 9
I
2
S Channel Mapping .................................................................................................................................................... 9
Control and Configuration .............................................................................................................................................. 10
Registers/Configuration Logic .................................................................................................................................... 10
I
2
C Ports ...................................................................................................................................................................... 10
Electrical Specifications ..................................................................................................................................................... 11
Absolute Maximum Conditions ...................................................................................................................................... 11
Normal Operating Conditions ......................................................................................................................................... 12
DC Specifications ........................................................................................................................................................... 13
Digital I/O Specifications ........................................................................................................................................... 13
DC Power Supply Specifications ................................................................................................................................ 14
AC Specifications ........................................................................................................................................................... 15
Video AC Timing Specifications ................................................................................................................................ 15
Interrupt Timings ........................................................................................................................................................ 17
Audio AC Timing Specifications ............................................................................................................................... 18
Timing Diagrams ................................................................................................................................................................ 20
TMDS Input Timing Diagrams ...................................................................................................................................... 20
Power Supply Control Timings ...................................................................................................................................... 20
Power Supply Sequencing .......................................................................................................................................... 20
Configuring Standby Power Mode ............................................................................................................................. 20
Digital Video Output Timing Diagrams ......................................................................................................................... 21
Calculating Setup and Hold Times ................................................................................................................................. 22
24-Bit SDR Mode ....................................................................................................................................................... 22
12-Bit DDR Mode ...................................................................................................................................................... 22
Audio Output Timings ................................................................................................................................................ 23
Control Timings .............................................................................................................................................................. 24
Reset Timings ............................................................................................................................................................. 24
Pin Descriptions .................................................................................................................................................................. 25
Digital Video Output Pins .............................................................................................................................................. 25
Digital Audio Output Pins .............................................................................................................................................. 26
Configuration/Programming Pins ................................................................................................................................... 26
Differential Signal Data Pins .......................................................................................................................................... 27
Power and Ground Pins .................................................................................................................................................. 27
Silicon Image
Confidential
for
PEARMAIN Electronics
Internal Use Only
SiI9013 HDMI Receiver
Data Sheet
Silicon Image, Inc.
iv © 2008-2010 Silicon Image, Inc. All rights reserved. SiI-DS-0232-D01
CONFIDENTIAL
Video Path .......................................................................................................................................................................... 28
HDMI Input Modes to SiI9013 HDMI Receiver Output Modes .................................................................................... 28
HDMI RGB 4:4:4 Input Processing ............................................................................................................................ 29
HDMI YCbCr 4:4:4 Input Processing ........................................................................................................................ 30
HDMI YCbCr 4:2:2 Input Processing ........................................................................................................................ 31
SiI9013 HDMI Receiver Output Mode Configuration ................................................................................................... 32
RGB and YCbCr 4:4:4 Formats with Separate Syncs................................................................................................. 33
YC 4:2:2 Formats with Separate Syncs ...................................................................................................................... 34
YC 4:2:2 Formats with Embedded Syncs ................................................................................................................... 35
YC Mux (4:2:2) Formats with Separate Syncs ........................................................................................................... 36
YC Mux 4:2:2 Formats with Embedded Syncs........................................................................................................... 37
48-Bit Output Mode .................................................................................................................................................... 38
12-Bit DDR RGB 4:4:4 and YCbCr 4:4:4 Formats with Separate Syncs ................................................................... 39
I
2
C Interfaces ...................................................................................................................................................................... 40
HDCP E-DDC / I
2
C Interface ......................................................................................................................................... 40
Local I
2
C Interface .......................................................................................................................................................... 41
Video Requirement for I
2
C Access ................................................................................................................................. 41
HDCP Registers .............................................................................................................................................................. 41
Design Recommendations .................................................................................................................................................. 42
Power Control ................................................................................................................................................................. 42
Power Pin Current Demands ....................................................................................................................................... 42
Crystal Clock Source Requirement ................................................................................................................................. 42
Receiver DDC Bus Protection ........................................................................................................................................ 42
PWR5V Input ................................................................................................................................................................. 43
Voltage Ripple Regulation .............................................................................................................................................. 43
Decoupling Capacitors .................................................................................................................................................... 43
Receiver Layout .............................................................................................................................................................. 43
ESD Protection ............................................................................................................................................................... 44
EMI Considerations ........................................................................................................................................................ 44
Thermal and Electrical Benefits of Exposed Pads .......................................................................................................... 45
Typical Circuits .............................................................................................................................................................. 45
Power Supply Decoupling .......................................................................................................................................... 45
HDMI Port TMDS Connections ................................................................................................................................. 46
Digital Video Output Connections .............................................................................................................................. 46
Digital Audio Output Connections ............................................................................................................................. 47
Control Signal Connections ........................................................................................................................................ 48
Layout ............................................................................................................................................................................. 48
TMDS Input Port Connections ................................................................................................................................... 49
Routing with ESD Devices ......................................................................................................................................... 49
Packaging ............................................................................................................................................................................ 50
Package Dimensions ....................................................................................................................................................... 50
Marking Specification..................................................................................................................................................... 51
Ordering Information .......................................................................................................................................................... 51
References .......................................................................................................................................................................... 52
Standards Documents ..................................................................................................................................................... 52
Silicon Image Documents ............................................................................................................................................... 52
Silicon Image
Confidential
for
PEARMAIN Electronics
Internal Use Only
SiI9013 HDMI Receiver
Data Sheet
Silicon Image, Inc.
SiI-DS-0232-D01 © 2008-2010 Silicon Image, Inc. All rights reserved. v
CONFIDENTIAL
List of Figures
Figure 1. DTV Block Diagram ............................................................................................................................................. 1
Figure 2. Pin Diagram .......................................................................................................................................................... 3
Figure 3. DTV Block Diagram ............................................................................................................................................. 4
Figure 4. Functional Block Diagram .................................................................................................................................... 5
Figure 5. Default Video Processing Path .............................................................................................................................. 6
Figure 6. I
2
C Register Domains .......................................................................................................................................... 10
Figure 7. Test Point VCCTP for VCC Noise Tolerance Spec ............................................................................................ 12
Figure 8. SCDT and CKDT Timing from DE or RXC Inactive/Active ............................................................................. 17
Figure 9. Audio Crystal Schematic ..................................................................................................................................... 18
Figure 10. TMDS Channel-to-Channel Skew Timing ........................................................................................................ 20
Figure 11. Power Supply Sequencing ................................................................................................................................. 20
Figure 12. Configuring Standby Power Mode .................................................................................................................... 20
Figure 13. Video Digital Output Transition Times ............................................................................................................. 21
Figure 14. Receiver Clock-to-Output Delay and Duty Cycle Limits .................................................................................. 21
Figure 15. 24-Bit SDR Mode Receiver Output Setup and Hold Times .............................................................................. 22
Figure 16. 12-Bit DDR Mode Receiver Output Setup and Hold Times ............................................................................. 23
Figure 17. I
2
S Output Timings ............................................................................................................................................ 23
Figure 18. S/PDIF Output Timings..................................................................................................................................... 23
Figure 19. MCLK Timings ................................................................................................................................................. 24
Figure 20. RESET# Minimum Timings ............................................................................................................................. 24
Figure 21. Receiver Video and Audio Data Processing Paths ............................................................................................ 28
Figure 22. HDMI RGB 4:4:4 Input to Video Output Transformations .............................................................................. 29
Figure 23. HDMI YCbCr 4:4:4 Input to Video Output Transformations ........................................................................... 30
Figure 24. HDMI YCbCr 4:2:2 Input to Video Output Transformations ........................................................................... 31
Figure 25. 4:4:4 Timing Diagram ....................................................................................................................................... 33
Figure 26. YC Timing Diagram .......................................................................................................................................... 34
Figure 27. YC 4:2:2 Embedded Sync Timing Diagram...................................................................................................... 35
Figure 28. YC Mux 4:2:2 Timing Diagram ........................................................................................................................ 36
Figure 29. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram ............................................................................. 37
Figure 30. 48-Bit 4:4:4 Timing Diagram ............................................................................................................................ 38
Figure 31. 12-Bit DDR Output 4:4:4 Timing Diagram ...................................................................................................... 39
Figure 32. I
2
C Byte Read .................................................................................................................................................... 40
Figure 33. I
2
C Byte Write ................................................................................................................................................... 40
Figure 34. Short Read Sequence ......................................................................................................................................... 40
Figure 35. Decoupling and Bypass Capacitor Placement ................................................................................................... 43
Figure 36. HDMI to Receiver Routing – Top View ........................................................................................................... 44
Figure 37. Power Supply Decoupling and PLL Filtering Schematic .................................................................................. 45
Figure 38. HDMI Port Connections Schematic .................................................................................................................. 46
Figure 39. Digital Display Schematic ................................................................................................................................. 47
Figure 40. Audio Output Schematic ................................................................................................................................... 47
Figure 41. XTALIN Connection with External Clock Source ............................................................................................ 48
Figure 42. Controller Connections Schematic .................................................................................................................... 48
Figure 43. TMDS Input Signal Assignments ...................................................................................................................... 49
Figure 44. TMDS Input Layout through ESD Devices ...................................................................................................... 49
Figure 45. Package Diagram ............................................................................................................................................... 50
Figure 46. Marking Diagram .............................................................................................................................................. 51
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