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Intel romley 平台规范
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英特尔romley平台规范,用于Intel romle平台设计，里面包含高速差分对走线规则，DDR3等长走线规则
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Reference Number: 441694 Revision: 1.1
Romley Platform
Design Guide
April 2011
Intel Confidential
2 Reference Number: 441694, Revision: 1.1
Intel Confidential
Legal Lines and Discla imers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
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life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Romley platform and its components may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
The code names “Romley,” “Sandy Bridge,” “Rose City,” “Harbor City,” “Potter City,” “Barton Hill,” “Patsburg,” “Westerlee,”
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enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For
more information including details on which processors support HT Technology, see
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I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed
by Intel. Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
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*Other names and brands may be claimed as the property of others.
Copyright © 2009-2011, Intel Corporation. All Rights Reserved.
Notice: This document contains information on products in the design phase of development. The information here is subject to change without
notice. Do not finalize a design with this information.
Reference Number: 441694, Revision: 1.1 3
Intel Confidential
Contents
1 Introduction and Overview...................................................................................... 35
1.1 Romley Platform Overview.................................................................................. 36
2 Romley Platform Stack-up, Placement and PCB Guidelines ...................................... 39
2.1 Romley Board Stack-Ups .................................................................................... 39
2.1.1 Romley Platform 6-Layer 1080 Stack-up.................................................. 39
2.1.2 Romley Platform 8-Layer 1080 Stack-up.................................................. 40
2.1.3 Romley Platform 10-Layer 1080 Stack-up ................................................ 40
2.1.4 Romley Platform 14-Layer 1080 Stack-up ................................................ 42
2.2 Romley Platform Common Field Solved Impedance Table........................................ 43
2.3 High-Speed PCB Loss......................................................................................... 44
2.3.1 High Speed Differential Loss Magnitude Requirement ................................ 44
2.3.2 Insertion Loss Measurement Recommendations ........................................ 44
2.3.3 Humidity Impact on Loss ....................................................................... 47
2.4 Component Quadrant Layouts ............................................................................. 48
2.4.1 Sandy Bridge-EP/EP 4S Processor Quadrant Layout................................... 49
2.4.2 Sandy Bridge-EN Processor Quadrant Layout............................................ 50
2.4.3 Patsburg PCH Quadrant Layout............................................................... 51
3 General High Speed Guidelines................................................................................ 53
3.1 Length Matching Requirements ........................................................................... 54
3.2 Routing Clearance from Vertical Features ............................................................. 64
3.3 Controlling Voltage Regulator (VR) Noise .............................................................. 64
3.4 Reference Plane ................................................................................................ 70
3.5 Escape Routing ................................................................................................. 72
3.6 Routing Through Pin Field................................................................................... 77
3.7 Layer Transitions and Via Stubs .......................................................................... 80
3.8 Connector Routing Guideline............................................................................... 86
3.9 Routing Under Connector Foot-print..................................................................... 88
3.10 AC Coupling Placement ...................................................................................... 89
3.11 PCIe and DMI2 General Routing Guidelines ........................................................... 90
3.12 Signal Integrity Guidelines.................................................................................. 92
4 Platform Clocking .................................................................................................... 97
4.1 Intel® QuickPath Interconnect and Memory Interface Clocking................................ 97
4.1.1 PCI Express* Clocking........................................................................... 97
4.1.2 I/O Clocking and Miscellaneous Clocking.................................................. 97
4.2 CK420BQ, CK-MNG, and DB1900Z Operational Settings.......................................... 99
4.3 General Routing Guidelines for Clocks ................................................................ 100
4.3.1 Reference Clock Routing Rules ............................................................. 100
4.3.2 Length Matching and Common Buffer Guidelines..................................... 102
4.4 Reference Board Topology Examples.................................................................. 102
4.4.1 Cascaded Clock Topologies .................................................................. 102
4.4.2 PCI Express Reference Clock Topologies ................................................ 104
4.4.3 Intel® QPI Reference Clock Topologies.................................................. 114
4.4.4 Other Reference Clock Topologies ......................................................... 116
4.5 CK-MNG/CK-MNG+ Clock Synthesizer ................................................................ 122
4.6 Single Ended Reference Clock Signals and Topologies........................................... 122
4.6.1 50 MHz RMII Reference Clock Topology ................................................. 123
4.6.2 CLK48 MHz Clock Group ...................................................................... 123
4.6.3 Topology for CLK48 ............................................................................ 124
4.6.4 CLK33 Clock Group............................................................................. 124
4.6.5 Topology for CLK33 ............................................................................ 125
4.6.6 Sharing 33-MHz Clocks........................................................................ 126
4 Reference Number: 441694, Revision: 1.1
Intel Confidential
4.6.7 25 MHz Reference Clock Topology .........................................................127
4.7 CLK14 Group................................................................................................... 128
4.7.1 Single Load Topology for CLK14 ............................................................ 128
4.7.2 Two Load Topology for CLK14...............................................................129
4.8 Clock Driver Decoupling....................................................................................129
4.9 Clock Power Delivery........................................................................................130
4.10 CK420BQ Power Plane Filtering.......................................................................... 130
4.10.1 VDD Plane Filtering .............................................................................130
4.10.2 VDDA Plane Filtering ........................................................................... 130
4.10.3 VDD_48 Plane Filtering ........................................................................ 131
4.11 DB1900Z Power Plane Filtering .......................................................................... 131
4.12 EMI Constraints ............................................................................................... 132
4.13 Crystal Recommendation for CK420BQ ...............................................................132
4.13.1 Crystal Loading...................................................................................132
4.13.2 Crystal Placement and Connectivity .......................................................133
5 CPU Specific Guidelines..........................................................................................135
5.1 Sandy Bridge-EP/EP 4S CPU Socket_ID Strapping ................................................ 135
5.2 Sandy Bridge-EN/EP/EP 4S Processor Intel® QPI ................................................. 136
5.2.1 Intel® QPI Layout Topologies ...............................................................138
5.2.2 Intel® QPI Routing Guidelines ..............................................................146
5.2.3 Intel® QPI Signal Integrity Notes..........................................................149
5.2.4 Intel® QPI Miscellaneous Circuits.......................................................... 150
5.3 CPU Miscellaneous Signals Overview................................................................... 151
5.3.1 CPU Miscellaneous Signals Routing Guidelines.........................................154
5.3.2 ERROR_N[2:0] and CAT_ERR_N Topology .............................................. 155
5.3.3 CPU_ONLY_RESET Topology .................................................................157
5.3.4 IVT_ID_N and SKTOCC_N Topology....................................................... 159
5.3.5 PMSYNC Topology and Guidelines.......................................................... 159
5.3.6 PROCHOT_N Topology and Guidelines....................................................160
5.3.7 THERMTRIP_N Topology and Guidelines ................................................. 161
5.3.8 PWRGOOD Topology and Guideline........................................................ 161
5.3.9 RESET_N Topology and Guidelines ........................................................162
5.3.10 CPU SMBus ........................................................................................163
5.3.11 SVID Topology and Guidelines ..............................................................165
6 Sandy Bridge-EP/EP 4S Processor Memory Routing Guidelines.............................. 167
6.1 Sandy Bridge-EP/EP 4S Processor DIMM Connector Layout ....................................169
6.2 Stackup and Referencing Guidelines ...................................................................170
6.3 DIMM Population Requirements .........................................................................170
6.3.1 General Population Requirements..........................................................170
6.3.2 Populating DIMMs Within a Channel....................................................... 172
6.3.3 Population Requirements for Memory RAS Modes ....................................178
6.4 DDR3 Design Topologies and Guidelines.............................................................. 179
6.4.1 Three DIMM Slot Per Channel Guidelines (LRDIMM/UDIMM/RDIMM) ........... 179
6.4.2 Two DIMM Slot Per Channel Guidelines
(LRDIMM/UDIMM/RDIMM)....................................................................194
6.4.3 One DIMM Slot Per Channel Guidelines (LRDIMM/UDIMM/RDIMM) ............. 202
6.4.4 Miscellaneous DDR3 Signals .................................................................210
6.5 DIMM Connector.............................................................................................. 218
7 Sandy Bridge-EN Processor Memory Routing Guidelines ........................................219
7.1 Sandy Bridge-EN Processor DIMM Connector Layout .............................................220
7.2 Stack-Up and Referencing Guidelines.................................................................. 221
7.3 DIMM Population Requirements .........................................................................221
7.3.1 General Population Requirements..........................................................221
7.3.2 Populating DIMMs Within a Channel....................................................... 223
7.3.3 Population Requirements for Memory RAS Modes ....................................226
Reference Number: 441694, Revision: 1.1 5
Intel Confidential
7.4 DDR3 Design Topologies and Guidelines ............................................................. 227
7.4.1 Channel Routing Restrictions................................................................ 228
7.4.2 Strobe Mapping and Clock Groups......................................................... 228
7.4.3 Two DIMM Slot Per Channel Guidelines (LRDIMM/UDIMM/RDIMM)............. 229
7.4.4 One DIMM Slot Per Channel Guidelines (LRDIMM/UDIMM/RDIMM) ............. 237
7.4.5 Miscellaneous DDR3 Signals................................................................. 245
7.5 DIMM Connector ............................................................................................. 253
8 Sandy Bridge Processor I/O Interface Guidelines.................................................. 255
8.1 Sandy Bridge-EP/EP 4S Processor PCIe Interface Guidelines.................................. 255
8.1.1 PCIe Test Points and Probing................................................................ 259
8.1.2 PCIe Connectors................................................................................. 259
8.1.3 Sandy Bridge-EP/EP 4S Processor PCIe Hot-Plug..................................... 260
8.1.4 Sandy Bridge-EP/EP 4S Processor PCIe, Termination of
Unused PCIe Ports .............................................................................. 260
8.1.5 Sandy Bridge-EP/EP 4S Processor PCIe PE_VREF_CAP ............................. 260
8.1.6 Sandy Bridge-EP/EP 4S Processor PCIe PE_RBIAS and
PERBIAS_SENSE Signal Guidelines........................................................ 261
8.1.7 Sandy Bridge-EP/EP 4S Processor Direct Media Interface (DMI2) .............. 262
8.2 Sandy Bridge-EP/EP 4S PCIe Layout Design Guidelines......................................... 263
8.2.1 One Connector Transmit Guidelines....................................................... 264
8.2.2 One Connector Receive Guidelines ........................................................ 268
8.2.3 One Connector with LAI Transmit/Receive Routing Guidelines................... 270
8.2.4 Two Connector Transmit Routing Guidelines ........................................... 271
8.2.5 Two Connector Receive Routing Guidelines ............................................ 275
8.2.6 Processor to Down Device Transmit/Receive Routing Guidelines................ 281
8.2.7 Processor to Down Device with LAI Transmit Routing Guidelines ............... 282
8.2.8 Processor to Down Device with LAI Receive Routing Guidelines................. 284
8.3 Sandy Bridge-EN Processor PCIe3 Interface Guidelines......................................... 285
8.3.1 PCIe Layout Design Guidelines ............................................................. 285
8.3.2 PCIe and DMI2 Test Points and Probing ................................................. 287
8.3.3 Connectors ........................................................................................ 287
8.3.4 Sandy Bridge-EN Processor PCIe3 Interface ........................................... 287
8.3.5 Sandy Bridge-EN Processor PCIe Hot Plug.............................................. 290
8.3.6 Sandy Bridge-EN Processor PCIe, Termination of
Unused PCIe Ports .............................................................................. 290
8.3.7 Sandy Bridge-EN Processor PCIe PE_VREF_CAP ...................................... 291
8.3.8 Sandy Bridge-EN Processor PCIe PE_RBIAS and
PERBIAS_SENSE Signal Guidelines........................................................ 291
8.3.9 Sandy Bridge-EN Processor Direct Media Interface (DMI2) ....................... 292
8.3.10 Sandy Bridge-EN Processor PCIe3 Connector
Interface Guidelines............................................................................ 292
8.3.11 Sandy Bridge-EN Processor to a PCIe3/PCIe2 Down
Device .............................................................................................. 316
9 Patsburg PCH Specific Guidelines .......................................................................... 323
9.1 Patsburg PCH Sideband Signals ......................................................................... 323
9.1.1 CPU CMOS Considerations ................................................................... 323
9.1.2 RCIN# and A20GATE Design Consideration ............................................ 324
9.1.3 PROCPWRGD Design Consideration ....................................................... 324
9.1.4 PM_SYNC, PM_SYNC2 Design Consideration ........................................... 324
9.1.5 THRMTRIP# Design Consideration......................................................... 324
9.1.6 Patsburg PCH V_CPU_IO Outputs.......................................................... 325
9.2 Patsburg PCH – Critical Low Speed Signals.......................................................... 325
9.2.1 General Design Consideration............................................................... 326
9.3 Patsburg PCH Interrupt Interface....................................................................... 327
9.3.1 PIRQ Example.................................................................................... 327
9.4 Patsburg PCH RTC ........................................................................................... 328
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