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Copyright © 2013, 2014 ARM Limited. All rights reserved.
ARM DDI 0487A.e (ID121714)
ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile
Beta
ii Copyright © 2013, 2014 ARM Limited. All rights reserved. ARM DDI 0487A.e
Non-Confidential - Beta ID121714
ARM Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile
Copyright © 2013, 2014 ARM Limited. All rights reserved.
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The following releases of this document have been made.
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.
Release history
Date Issue Confidentiality Change
30 April 2013 A.a-1 Confidential-Beta Draft Beta draft of first issue, limited circulation
12 June 2013 A.a-2 Confidential-Beta Draft Second beta draft of first issue, limited circulation
04 September 2013 A.a Non-Confidential Beta Beta release.
24 December 3013 A.b Non-Confidential Beta Second beta release.
18 July 2014 A.c Non-Confidential Beta Third beta release.
09 October 2014 A.d Non-Confidential Beta Fourth beta release.
17 December 2014 A.e Non-Confidential Beta Fifth beta release.
ARM DDI 0487A.e Copyright © 2013, 2014 ARM Limited. All rights reserved. iii
ID121714 Non-Confidential - Beta
This document is Non-Confidential but any disclosure by you is subject to you providing the recipient the conditions set out in
this notice and procuring the acceptance by the recipient of the conditions set out in this notice.
Copyright © 2013, 2014 ARM Limited or its affiliates. All rights reserved.
ARM Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20327
In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as appropriate”.
Note
• The term ARM can refer to versions of the ARM architecture, for example ARMv8 refers to version 8 of the ARM
architecture. The context makes it clear when the term is used in this way.
• This document describes only the ARMv8-A architecture profile. For the behaviors required by the ARMv7-A and
ARMv7-R architecture profiles, see the ARM
®
Architecture Reference Manual, ARMv7-A and ARMv7-R edition.
Web Address
http://www.arm.com
Limitations of issue A.e
This issue A.e of the ARMv8 Architecture Reference Manual contains many improvements and corrections. However, as
indicated by its beta status, it remains work-in-progress. Validation of this document has identified the following issues that ARM
will address in the next issue:
• Compared to changes made in issue A.d:
—The ARM Generic Interrupt Controller (GICv3) CPU interface register descriptions in
Chapter D7 AArch64
System Register Descriptions
and Chapter G6 AArch32 System Register Descriptions have been updated
significantly, but are still work-in-progress, and remain as alpha quality and subject to change. Contact ARM if you
require more information about these registers.
— We are in the process of improving the introductory A64 instruction descriptions in
Chapter C6 A64 Base
Instruction Descriptions
and Chapter C7 A64 Advanced SIMD and Floating-point Instruction
Descriptions. However, this work is incomplete and many instructions still have only a minimal introduction.
— The subsections on Traps and enables in the System register descriptions in
Chapter D7 AArch64 System
Register Descriptions
and Chapter G6 AArch32 System Register Descriptions, that were added in issue
A.d, have been significantly revised. These revisions have not had the same level of review as the rest of the
manual.
• We are working to improve the descriptions of register reset behavior in the register descriptions throughout this manual.
For issue A.e we have concentrated on the AArch32 System registers described in
Chapter G6 AArch32 System
Register Descriptions
, excluding the GICv3 CPU interface registers and the debug registers.
Note
Except for the registers mentioned in this bullet, the register descriptions do not give a clear indication of when any stated
reset values apply.
PE state on reset to AArch64 state on page D1-1512 summarizes the requirements for a reset into
AArch64 state, but there is no equivalent summary for a reset into AArch32 state.
• There have been additions to the Performance Monitors Extension described in Chapter D5 The Performance
Monitors Extension. These additions include the definition of additional events, described in Chapter D5, and
additional recommended
IMPLEMENTATION DEFINED events, described in Appendix J3 Recommendations for
Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
. These additions have had
only very limited review. In addition, while we believe
Appendix J3 lists all of the new recommended IMPLEMENTATION
DEFINED events, it does not yet describe the new events.
iv Copyright © 2013, 2014 ARM Limited. All rights reserved. ARM DDI 0487A.e
Non-Confidential - Beta ID121714
ARM DDI 0487A.e Copyright © 2013, 2014 ARM Limited. All rights reserved. v
ID121714 Non-Confidential - Beta
Contents
ARM Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile
Preface
About this manual ..................................................................................................... xvi
Using this manual .................................................................................................... xviii
Conventions ............................................................................................................ xxiii
Additional reading .................................................................................................... xxv
Feedback ................................................................................................................ xxvi
Part A ARMv8 Architecture Introduction and Overview
Chapter A1 Introduction to the ARMv8 Architecture
A1.1 About the ARM architecture ................................................................................ A1-30
A1.2 Architecture profiles ............................................................................................ A1-32
A1.3 ARMv8 architectural concepts ............................................................................. A1-33
A1.4 Supported data types .......................................................................................... A1-36
A1.5 Floating-point and Advanced SIMD support ........................................................ A1-46
A1.6 Cryptographic Extension ..................................................................................... A1-52
A1.7 The ARM memory model .................................................................................... A1-53
Part B The AArch64 Application Level Architecture
Chapter B1 The AArch64 Application Level Programmers’ Model
B1.1 About the Application level programmers’ model ................................................ B1-58
B1.2 Registers in AArch64 Execution state ................................................................. B1-59
B1.3 Software control features and EL0 ...................................................................... B1-65
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