FS32K144UAT0VLLT参考手册(2018.1)_fs32k144hrvll,fs32k144hrvll中文手册

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S32K1xx Series Reference Manual

Supports S32K116, S32K118, S32K142, S32K144, S32K146, and

S32K148

Document Number: S32K1XXRM

Rev. 6, 12/2017

Preliminary

Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 49

1.2 Organization..................................................................................................................................................................49

1.3 Module descriptions......................................................................................................................................................49

1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 50

1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 51

1.4 Register descriptions.....................................................................................................................................................52

1.5 Conventions.................................................................................................................................................................. 53

1.5.1 Notes, Cautions, and Warnings......................................................................................................................53

1.5.2 Numbering systems........................................................................................................................................53

1.5.3 Typographic notation..................................................................................................................................... 54

1.5.4 Special terms..................................................................................................................................................54

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................57

2.2 S32K1xx Series introduction........................................................................................................................................57

2.2.1 S32K14x.........................................................................................................................................................57

2.2.2 S32K11x ........................................................................................................................................................58

2.3 Feature summary...........................................................................................................................................................59

2.4 Block diagram...............................................................................................................................................................62

2.5 Feature comparison.......................................................................................................................................................64

2.6 Applications..................................................................................................................................................................66

2.7 Module functional categories........................................................................................................................................67

2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................68

2.7.2 Arm Cortex-M0+ Core Modules....................................................................................................................69

2.7.3 System modules............................................................................................................................................. 69

2.7.4 Memories and memory interfaces..................................................................................................................70

S32K1xx Series Reference Manual, Rev. 6, 12/2017

NXP Semiconductors

Preliminary

Section number Title Page

2.7.5 Power Management........................................................................................................................................71

2.7.6 Clocking.........................................................................................................................................................71

2.7.7 Analog modules............................................................................................................................................. 72

2.7.8 Timer modules............................................................................................................................................... 72

2.7.9 Communication interfaces............................................................................................................................. 73

2.7.10 Debug modules.............................................................................................................................................. 73

Chapter 3

Memory Map

3.1 Introduction...................................................................................................................................................................75

3.2 SRAM memory map.....................................................................................................................................................75

3.2.1 S32K14x: SRAM memory map ....................................................................................................................75

3.2.2 S32K11x: SRAM memory map ....................................................................................................................75

3.3 Flash memory map........................................................................................................................................................76

3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................76

3.4.1 Read-after-write sequence and required serialization of memory operations................................................77

3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................78

3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 79

Chapter 4

Signal Multiplexing and Pin Assignment

4.1 Introduction...................................................................................................................................................................81

4.2 Functional description...................................................................................................................................................81

4.3 Pad description..............................................................................................................................................................82

4.4 Default pad state........................................................................................................................................................... 83

4.5 Signal Multiplexing sheet............................................................................................................................................. 84

4.5.1 IO Signal Table ............................................................................................................................................. 84

4.5.2 Input muxing table......................................................................................................................................... 86

4.6 Pinout diagrams............................................................................................................................................................ 87

Chapter 5

Security Overview

5.1 Introduction...................................................................................................................................................................89

S32K1xx Series Reference Manual, Rev. 6, 12/2017

Preliminary

NXP Semiconductors

Section number Title Page

5.2 Device security..............................................................................................................................................................89

5.2.1 Flash memory security...................................................................................................................................89

5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................90

5.2.3 Device Boot modes........................................................................................................................................ 91

5.3 Security use case examples...........................................................................................................................................91

5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 91

5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 92

5.3.3 Secure communication...................................................................................................................................93

5.3.4 Component protection....................................................................................................................................94

5.3.5 Message-authentication example................................................................................................................... 95

5.4 Steps required before failure analysis...........................................................................................................................96

5.5 Security programming flow example (Secure Boot).................................................................................................... 97

Chapter 6

Safety Overview

6.1 Introduction...................................................................................................................................................................99

6.2 S32K1xx safety concept............................................................................................................................................... 100

6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................101

6.2.2 ECC on RAM and flash memory...................................................................................................................102

6.2.3 Power supply monitoring...............................................................................................................................102

6.2.4 Clock monitoring........................................................................................................................................... 103

6.2.5 Temporal protection.......................................................................................................................................103

6.2.6 Operational interference protection............................................................................................................... 103

6.2.7 CRC................................................................................................................................................................105

6.2.8 Diversity of system resources........................................................................................................................ 105

Chapter 7

CM4 Overview

7.1 Arm Cortex-M4F core configuration............................................................................................................................107

7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 108

7.1.2 System Tick Timer.........................................................................................................................................108

S32K1xx Series Reference Manual, Rev. 6, 12/2017

NXP Semiconductors

Preliminary