89c51单片机论文英文文献翻译_stc89c52单片机外文

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Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of

Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is

manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the

industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with

Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly

flexible and cost effective solution to many embedded control applications.

Features:

• Compatible with MCS-51™ Products

• 4K Bytes of In-System Reprogrammable Flash Memory

• Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz

• Three-Level Program Memory Lock

• 128 x 8-Bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-Bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low Power Idle and Power Down Modes

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32

I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial

port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for

operation down to zero frequency and supports two software selectable power saving modes. The Idle

Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to

continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator

disabling all other chip functions until the next hardware reset.

Block Diagram

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during

accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it

uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit

addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming

and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal

pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source

current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Port 3 also receives

some control signals for

Flash programming and

verification.

RST

Reset input. A high on

this pin for two machine

cycles while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to

external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during

each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT89C51 is executing code from external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each access to external data

memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code

Port pin alternate functions

P3.0 rxd (serial input port)

P3.1 txd (serial output port)

P3.2 ^int0 (external interrupt0)

P3.3 ^int1 (external interrupt1)

P3.4 t0 (timer0 external input)

P3.5 t1 (timer1 external input)

P3.6 ^WR (external data memory write strobe)

P3.7 ^rd (external data memory read strobe)

from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit

1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming,

for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be

configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic

resonator may be used. To drive the device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle

of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two

flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode

is invoked by software. The content of the on-chip RAM and all the special functions registers remain

unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a

hardware reset.

It should be noted that when idle is terminated by a hard ware reset, the device normally resumes

program execution, from where it left off, up to two machine cycles before the internal reset algorithm

takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins

is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated

by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or

to external memory.

Status of External Pins During Idle and Power Down Modes

mode Program memory ALE ^psen Port0 Port1 Port2 Port3

idle internal 1

data data data Data

Idle External 1 1 float Data data Data

Power down Internal 0 0 Data Data Data Data

Power down External 0 0 float data Data data

Power Down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes power down is

the last instruction executed. The on-chip RAM and Special Function Registers retain their values until

the power down mode is terminated. The only exit from power down is a hardware reset. Reset

redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before

VCC is restored to its normal operating level and must be held active long enough to allow the oscillator

to restart and stabilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to

obtain the additional features listed in the table below:

Lock Bit Protection Modes

Program lock bits Protection type

Lb1 Lb2 Lb3

1 U U U No program lock features

2 P U U Movc instructions executed from external program memory are

disable from fetching code bytes from internal memory, ^ea is

sampled and latched on reset, and further programming of the flash

disabled

3 P P U Same as mode 2, also verify is disable.

4 P P P Same as mode 3, also external execution is disabled.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.

If the device is powered up without a reset, the latch initializes to a random value, and holds that value

until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic

level at that pin in order for the device to function properly.

Programming the Flash：

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is,

contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage

(12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides

a convenient way to program the AT89C51 inside the user’s system, while the high-voltage

programming mode is compatible with conventional third party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.

The respective top-side marking and device signature codes are listed in the following table.

Vpp=12v Vpp=5v

Top-side mark AT89C51

xxxx

yyww

AT89C51

xxxx-5

yyww

signature (030H)=1EH (030H)=1EH

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2014-08-09

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