Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 3
UG585 (v1.7) February 11, 2014
08/08/2012 1.2 Added information about the 7z010 CLG225 device and references to section
2.5.4 MIO-at-a-Glance Table throughout document.
Added section headings
1.1.1 Block Diagram and 1.1.2 Documentation Resources, added sections 1.1.3 Notices
and TrustZone Capabilities, and clarified PS MIO I/Os in Chapter 1. Updated Table 2-1.
Changed 2.4.2 MIO-EMIO Connections heading to 2.5.2 IOP Interface Connections and
clarified first paragraph. Updated Table 2-4. Added section 2.7.1 Clocks and Resets and
Table 2-7, and updated Table 2-13 PS MIO I/Os in Chapter 2. Added note under Branch
Prediction and Table 3-8 in Chapter 3. Updated Table 4-1 in Chapter 4. Added section
5.1.7 Read/Write Request Capability in Chapter 5. Updated
NAND Boot MIO pin
assignments and
Table 6-6 in Chapter 6. Updated section 7.1.5 CPU Interrupt Signal
Pass-through in Chapter 7. Added section heading 10.1.1 Features and added section
10.1.3 Notices in Chapter 10. Updated Parallel (SRAM/NOR) Interface features list and
added section 11.1.3 Notices in Chapter 11. Reorganized, clarified, and expanded
Chapter 12 to include programming models (added sections 12.1.4 Notices,
12.3 Programming Guide, and 12.5.2 MIO Programming). Added last note in section
13.3.4 Using ADMA in Chapter 13. Added Restrictions in Chapter 14. Clarified first
paragraph, added section 15.1.3 Notices, and clarified Figure 15-7 through
Figure 15-17 in Chapter 15. Added section 16.1.4 Notices in Chapter 16. Clarified
sections 17.2.5 SPI FIFOs, 17.2.6 SPI Clocks, and 17.2.7 SPI EMIO Considerations in
Chapter 17. Reorganized, clarified, and expanded Chapter 18 to include programming
models (added sections 18.1.4 Notices and 18.5.1 MIO Programming). Reorganized,
clarified, and expanded Chapter 19 to include programming models (added sections
19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated
Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in
Chapter 25. Updated Table 26-4 in Chapter 26. Clarified section 27.3 I/O Signals in
Chapter 27. Added section 28.1.2 Notices in Chapter 28. Clarified Mapping Summary
and updated
Table 29-1, Table 29-3, and Ta b l e 29-5 in Chapter 29. Added section
30.1.3 Notices in Chapter 30. Updated data sheet references in section A.3.1 Zynq-7000
AP SoC Documents of Appendix A. Updated register database in sections B.3 Module
Summary through B.34 USB Controller (usb) in Appendix B.
10/30/2012 1.3 Changed product name from Extensible Processing Platform (EPP) to All Programmable
SoC (AP SoC) throughout document. Added Ta b l e 1-1. Added 2.1.1 Notices, 2.4 PS–PL
Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in
Table 2-2., VREF Source Considerations, updated Table 2 - 2 , and added warning to
2.5.7 MIO Pin Electrical Parameters. Added Initialization of L1 Caches, 3.2.4 Memory
Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown
by Way Sequence and 3.9 CPU Initialization Sequence. Added Zynq-7000 AP SoC 7z010
CLG225 Device Notice and expanded Table 4-7. Updated and expanded tables in
6.3.4 Quad-SPI Boot through 6.3.12 Post BootROM State, reworked 6.3.6 Debug Status,
and added 6.3.12 Post BootROM State and AXI and DMA Done Status Interrupts.
Reworked Table 7-3. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and
Reset. Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices,
expanded 10.1.6 I/O Signals, added 10.6.11 DRAM Write Latency Restriction,
10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes.
Added 12.2.4 I/O Mode Considerations and updated 12.3.5 Rx/Tx FIFO Response to I/O
Command Sequences
. Reworked 16.3.3 I/O Configuration, added 16.4 IEEE 1588 Time
Stamping and 16.6.7 MIO Pin Considerations. Added 18.2.7 CAN0-to-CAN1
Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added
Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UART0-to-UART1
Connection and 19.2.10 Status and Interrupts, expanded 19.2.11 Modem Control,
reworked 19.3 Programming Guide and 19.4.2 Resets. Added 20.2.7 I2C0-to-I2C1
Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and
reorganized content of Chapter 21, Programmable Logic Description. Added
25.7.1 Clock Throttle. Expanded 26.4.1 PL General Purpose User Resets. Updated
register database in sections B.3 Module Summary through B.34 USB Controller (usb)
in Appendix B.
11/16/2012 1.4 Changed second bullet under NAND Flash Interface from “
Up to a 4 GB device” to “Up
to a 1 GB device” in
Chapter 11, Static Memory Controller.
Date Version Revision
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