PCI Express Base Specification, Rev. 4.0 Version 1.0
2
Revision Revision History Date
Incorporated Errata C1-C66 and E1-E4.17.
Incorporated approved Errata and ECNs.
Added 5.0 GT/s data rate and incorporated approved Errata and ECNs.
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and approved by
PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated
June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
•
TLP Prefix ECN (December 15, 2008)
03/04/2009
Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs:
• Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009)
• ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009)
• Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol
Multiplexing ECN (17 June 2010)
3.1 Incorporated feedback from Member Review
Incorporated Errata for the PCI Express® Base Specification Revision 3.0
Incorporated M-PCIe Errata (3p1_active_errata_list_mpcie_28Aug2014.doc and
3p1_active_errata_list_mpcie_part2_11Sept2014.doc)
Incorporated the following ECNs:
• ECN: Downstream Port containment (DPC)
• ECN: Separate Refclk Independent SSC (SRIS) Architecture
• ECN: Process Address Space ID (PASID)
• ECN: Lightweight Notification (LN) Protocol
• ECN: Precision Time Measurement
• ECN: Enhanced DPC (eDPC)
• ECN: 8.0 GT/s Receiver Impedance
• ECN: L1 PM Substates with CLKREQ
• ECN: Change Root Complex Event Collector Class Code
• ECN: M-PCIe
• ECN: Readiness Notifications (RN)
• ECN: Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC
10/8/2014
3.1a Minor update:
Corrected: Equation 4.3.9 in Section 4.3.8.5., Separate Refclk With Independent SSC
(SRIS) Architecture. Added missing square (exponent=2) in the definition of B.
B = 2.2 × 10^12 × (2.π)^2 where ^= exponent.
12/5/2015
4.0 Version 0.3: Based on PCI Express® Base Specification Revision 3.1
(October 8, 2014) with some editorial feedback received in December 2013.
• Added Chapter 9, Electrical Sub-block: Added Chapter 9 (Rev0.3-11-30-
13_final.docx)
• Changes related to Revision 0.3 release
• Incorporated PCIe-relevant material from PCI Bus Power Management Interface
Specification (Revision 1.2, dated March 3, 2004). This initial integration of the
material will be updated as necessary and will supercede the standalone Power
Management Interface specification.
Version 0.5 (12/22/14, minor revisions on 1/26/15, minor corrections 2/6/15)
• Added front matter with notes on expected discussions and changes.
• Added ECN:Retimer (dated October 6, 2014)
• Corrected Chapter 4 title to, “Physical Layer Logical Block”.
• Added Encoding subteam feedback on Chapter 4
• Added Electrical work group changes from PCIe Electrical Specification Rev 0.5
RC1 into Chapter 9
Version 0.7: Based on PCI Express® Base Specification Version 4.0 Revision 0.5
(11/23/2015)
• Added ECN_DVSEC-2015-08-04
2/6/2015
11/24/2015
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