Allegro_PCB_SI一步一步学会前仿真_cadenceallegro如何更改线宽

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Allegro PCB SI：

一步一步学会前仿真

Learn Allegro PCB SI Pre-simulation Step by

Step

Doc Scope : Cadence 16.5

Doc Number : SFTEC12007

Author : Daniel Zhong

Create Date : 2012-04-10

Rev : 1.00

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目录
Cadence Allegro PCB SI简介...........................................................7
1  高速PCB设计流程................................................................................................................. 7
Allegro PCB SI的前仿真....................................................................8
1  准备仿真模型和其他需求........................................................................................................ 9
1.1   获取所使用元器件的仿真模型........................................................................................... 9
1.2  获取所使用连接器的仿真模型..........................................................................................10
1.3  获取所使用元器件和连接器的器件手册和用户指南等相关资料...............................................10
1.4  获取所需的规范文档....................................................................................................... 10
1.5  了解相关电路和接口工作原理..........................................................................................10
1.6  提取与信号完整性相关的要求..........................................................................................10
1.7  预先创建拓扑样本.......................................................................................................... 11
1.8  预先创建相对于不同阈值电压的眼图模板...........................................................................11
1.9  预先创建自定义测量....................................................................................................... 11
2  仿真前的规划..................................................................................................................... 12
3  关键器件预布局.................................................................................................................. 12
4  模型加载和仿真配置............................................................................................................ 13
4.1  模型的转化................................................................................................................... 13
4.2  使用SI Design Setup配置.............................................................................................. 15
4.3  选择需要配置的信号线....................................................................................................16
4.4  设置仿真库................................................................................................................... 18
4.5  设置电源和地网络.......................................................................................................... 20
4.6  设置叠层...................................................................................................................... 24
4.7  设置元器件类别............................................................................................................. 27
4.8  为元器件分配和创建模型.................................................................................................28
4.9  设置差分对................................................................................................................... 37
4.10  设置仿真参数.............................................................................................................. 42
4.11  SI Design Audit相关...................................................................................................51
4.12  提取拓扑.................................................................................................................... 53
4.13  在SigXP中设置仿真库和仿真参数...................................................................................55
4.14  在SigXP中绘制拓扑.....................................................................................................59
5  方案空间分析..................................................................................................................... 69
5.1  输出驱动力扫描分析....................................................................................................... 72
5.2  Stub长度扫描分析......................................................................................................... 74
5.3  线宽线间距扫描分析....................................................................................................... 75
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2.6 方案到约束规则的转化......................................................................................................... 77

2.6.1 传输线延迟规则的设置....................................................................................................78

2.6.2 拓扑结构等传输线特性规则的设置....................................................................................81

2.6.3 传输线耦合规则的设置....................................................................................................81

2.6.4 拓扑规则在约束管理器中的应用.......................................................................................82

3 Allegro PCB SI的后仿真..................................................................85

表格

表格 1：Routed Interconnect Models参数.................................................................................................. 45

表格 2：Simulation栏眉仿真参数............................................................................................................ 48

表格 3：IO Cell Stimulus Edit窗口中的选项............................................................................................69

图

图 1：传统的PCB设计流程图................................................................................................................... 7

图 2：Allegro PCB SI高速PCB设计流程图................................................................................................8

图 3：眼图模式下的眼图模板................................................................................................................ 11

图 4：地址、命令和控制信号传输线拓扑...........................................................................................12

图 5：RDIMM的布局示意图..................................................................................................................... 13

图 6：Model Integrity界面........................................................................................................................... 14

图 7：使用Model Integrity将IBIS文件转换至DML格式...........................................................................15

图 8：Cadence Product Choices产品选择器窗口....................................................................................16

图 9：Allegro PCB SI GXL界面................................................................................................................... 17

图 10：Setup Category Selection窗口........................................................................................................ 17

图 11：Setup Xnet Selection窗口............................................................................................................... 17

图 12：Allegro PCB SI GXL关于网络设置的提醒框..............................................................................18

图 13：Setup Library Search Directories窗口............................................................................................. 19

图 14：Setup Library File Extensions窗口.................................................................................................. 19

图 15：Setup Working Libraries窗口.......................................................................................................... 19

图 16：Setup Power and Ground Nets窗口................................................................................................ 20

图 17：Allegro PCB SI GXL电压赋值窗口............................................................................................... 21

图 18：选择“Edit Voltage On Any Net In Design”....................................................................................... 21

图 19：Identify DC Nets窗口。.................................................................................................................. 22

图 20：Allegro PCB SI GXL关于电源和地网络的提醒框......................................................................22

图 21：设置电源和地网络环节的SI Design Audit窗口.........................................................................23

图 22：Select Errors to be Resolved窗口自动修复VTT问题...................................................................23

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图 23：Change Pin Use of a Pin窗口......................................................................................................... 24
图 24：选中管脚后的Change Pin Use of a Pin窗口................................................................................24
图 25：Setup Design Cross-Section窗口.................................................................................................... 25
图 26：JEDEC规范中的RDIMM RC B0叠层............................................................................................26
图 27：Layout Cross Section窗口............................................................................................................... 26
图 28：SI Design Audit窗口提示不合理的介电常数.............................................................................27
图 29：Setup Component Classes窗口...................................................................................................... 28
图 30：Assign Values to Discrete Components窗口...................................................................................29
图 31：Allegro PCB SI GXL分立元件赋值对话框...................................................................................29
图 32：Assign Models to Components窗口................................................................................................ 30
图 33：SI Model Browser窗口的DML Models栏眉...................................................................................31
图 34：Create Espice Device Model窗口.................................................................................................... 32
图 35：在Create IBIS Device Model窗口中创建金手指模型.................................................................32
图 36：在Create IBIS Device Model窗口中创建SPD模型......................................................................33
图 37：SI Design Audit窗口提示丢失的模型..........................................................................................33
图 38：Select Errors to be Resolved窗口自动修复模型丢失问题........................................................34
图 39：Signal Model Assignment窗口........................................................................................................ 35
图 40：SI Model Browser窗口中分配IBIS文件........................................................................................36
图 41：SI Model Browser窗口中分配IBIS器件........................................................................................37
图 42：Setup Diff Pairs窗口........................................................................................................................ 38
图 43：Setup Diff Pairs窗口中显示问题差分对.....................................................................................39
图 44：Change Diff Pair to be Defined by a Model窗口..............................................................................40
图 45：Change Diff Pair to be Defined by a Model窗口..............................................................................40
图 46：在SI Model Brower窗口中编辑IBIS器件......................................................................................41
图 47：在IBIS Device Model Editor窗口中选择管脚...............................................................................41
图 48：IBIS Device Pin Data窗口............................................................................................................... 42
图 49：IBIS Device Pin Data窗口中修改数据.......................................................................................... 42
图 50：Setup SI Simulations窗口............................................................................................................... 43
图 51：Setup Complete窗口....................................................................................................................... 43
图 52：Analysis Preferences窗口DevicesModels栏眉..............................................................................44
图 53：Analysis Preferences窗口InterconectModels栏眉.........................................................................44
图 54：EMS2D Preferences对话框............................................................................................................ 46
图 55：Via Model Extraction Setup窗口...................................................................................................... 46
图 56：Analysis Preferences窗口Simulation栏眉......................................................................................47
图 57：Analysis Preferences窗口S-Parameters栏眉................................................................................47
图 58：Set Advanced Measurement Parameters对话框............................................................................48
图 59：Fast/Typical/Slow Simulations Definition窗口.................................................................................48
图 60：Analysis Preferences窗口Units栏眉.............................................................................................. 49
图 61：Analysis Preferences窗口EMI栏眉................................................................................................ 49
图 62：Analysis Preferences窗口Power Integrity栏眉...............................................................................50
图 63：SI Design Audit窗口审核项目选择界面......................................................................................51
图 64：SI Design Audit窗口网络选择界面.............................................................................................. 52
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图 65：SI Design Audit窗口审核错误显示界面......................................................................................52
图 66：RDIMM上的预布线........................................................................................................................ 53
图 67：选择SI用户界面............................................................................................................................ 53
图 68：过滤器............................................................................................................................................ 53
图 69：查看拓扑........................................................................................................................................ 53
图 70：SigXplorer界面中显示网络拓扑.................................................................................................. 54
图 71：在Signal Analysis窗口选择网络提取拓扑.................................................................................. 54
图 72：Cadence Products Choices窗口..................................................................................................... 55
图 73：SI Model Browser窗口.................................................................................................................... 56
图 74：Set Model Search Path窗口............................................................................................................ 56
图 75：DML Library Management窗口....................................................................................................... 56
图 76：SI Model Browser窗口转换IBIS..................................................................................................... 56
图 77：LayerStack Manager窗口................................................................................................................ 57
图 78：导入叠层........................................................................................................................................ 57
图 79：选择来源文件............................................................................................................................... 57
图 80：命名叠层........................................................................................................................................ 57
图 81：Layout Cross Section窗口显示默认6层板叠层..........................................................................58
图 82：Pulse Stimulus栏眉......................................................................................................................... 58
图 83：S-Parameters栏眉........................................................................................................................... 58
图 84：Simulation Paremeters栏眉............................................................................................................ 59
图 85：Simulation Modes栏眉.................................................................................................................... 59
图 86：Measurement Modes栏眉............................................................................................................... 59
图 87：EMI栏眉.......................................................................................................................................... 59
图 88：Add Element Browser窗口中选择IbisDevice.................................................................................60
图 89：Add Element Browser窗口中选择寄存器芯片............................................................................60
图 90：Select IBIS Device Pin窗口中选择缓冲器模型...........................................................................61
图 91：在SigXplorer窗口中摆放缓冲器模型.........................................................................................61
图 92：在SigXplorer窗口中摆放电源模型.............................................................................................. 62
图 93：在SigXplorer窗口中摆放传输线模型.........................................................................................62
图 94：在SigXplorer窗口中摆放过孔模型.............................................................................................. 63
图 95：在SigXplorer窗口中电源参数值.................................................................................................. 63
图 96：在SigXplorer窗口中修改电阻阻值.............................................................................................. 64
图 97：View Trace Model Parameters窗口显示传输线参数...................................................................64
图 98：在SigXplorer窗口中修改传输线参数.........................................................................................65
图 99：在SigXplorer窗口中修改传输线所在层面.................................................................................65
图 100：在SigXplorer窗口中拷贝传输线模型.......................................................................................66
图 101：在SigXplorer窗口中拷贝和移动模型.......................................................................................66
图 102：在SigXplorer窗口中连接模型绘制拓扑...................................................................................67
图 103：在SigXplorer窗口中设置驱动器状态.......................................................................................67
图 104：在IO Cell Stimulus Edit窗口中设置伪随机码激励...................................................................68
图 105：在SigXplorer窗口中选择测量.................................................................................................... 69
图 106：最前端正面接收器眼图波形.................................................................................................... 70
Copyright @ 2005-2011 by Shanghai Sofer Technology Co., Ltd.