QSFP-DD管理接口协议_QSFPDD

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Common management specification Rev 3.0

Common Management Interface Specification

for

8X/16X PLUGGABLE TRANSCEIVERS

Rev 3.0 September 18, 2018

Abstract: This document defines the Common Management Interface Specification (CMIS)for

pluggable modules such as QSFP Double Density (QSFP-DD), OSFP and COBO. This document

provides a common specification for systems manufacturers, system integrators, and

suppliers of modules and transceivers.

POINTS OF CONTACT:

Tom Palkert Mark Nowell Scott Sommers

Technical Editor Co-Chair Co-Chair

Molex Cisco Molex

2222 Wellington Court 170 West Tasman Dr 2222 Wellington Court

Lisle, IL 60532-1682 San Jose, CA 95134 Lisle, IL 60532-1682

Ph: +1 (952)-200-8542 Ph: +1 (613)-254-3391 Ph: +1 (630)-527-4317

tom.palkert at molex.com mnowell at cisco.com scott.sommers at molex.com

Limitation on use of Information:

This specification is provided "AS IS" with NO WARRANTIES whatsoever and therefore the

provision of this specification does not include any warranty of merchantability,

noninfringement, fitness for a particular purpose, or any other warranty otherwise

arising out of any proposal, specification or sample. The authors further disclaim all

liability, including liability for infringement of any proprietary rights, relating to

use of information in this specification. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted herein.

Permissions:

You are authorized to download, reproduce and distribute this document. All other rights

are reserved. The provision of this document should not be construed as the granting of

any right to practice, make, use or otherwise develop products that are based on the

document. Any and all IP rights related to this document and the designs disclosed

within, except for the rights expressly mentioned above, are reserved by the respective

owners of those IP rights.

Common management specification Rev 3.0

CONTENTS

Management Interface ................................................................ 5

1.1 Introduction ....................................................................................................................................................................... 5

1.2 Definitions and Acronyms .......................................................................................................................................... 6

1.3 Management Interface Timing Specifications and Protocol ................................................................ 8

1.3.1 Introduction ............................................................................................................................................................... 8

1.3.2 Management Interface Timing Specification .......................................................................................... 8

1.3.3 Signal Interface ..................................................................................................................................................... 8

1.3.4 Serial Interface Protocol ................................................................................................................................ 8

1.3.5 Read/Write Operations ......................................................................................................................................... 9

1.3.6 Timing for Soft Control and Status Functions ................................................................................. 16

1.4 Module State Machine .................................................................................................................................................. 17

1.4.1 Module Init Modes ................................................................................................................................................. 20

1.4.2 Module Power Mode and Module and Data Path State Machine interactions ..................... 20

1.4.3 Reset State ............................................................................................................................................................... 21

1.4.4 MgmtInit State ........................................................................................................................................................ 22

1.4.5 ModuleLowPwr State ............................................................................................................................................... 22

1.4.6 ModulePwrUp state ................................................................................................................................................. 23

1.4.7 ModuleReady State ................................................................................................................................................. 23

1.4.8 ModulePwrDn State ................................................................................................................................................. 23

1.4.9 Fault State ............................................................................................................................................................... 24

1.5 Application/Data Path Overview .......................................................................................................................... 24

1.5.1 Host Electrical and Module Media Lane Background ....................................................................... 24

1.5.2 Application Advertising Methodology ...................................................................................................... 26

1.5.3 Data Path State Machine ................................................................................................................................... 31

1.5.4 Control Set Overview .......................................................................................................................................... 37

1.5.5 Signal Integrity Control Field Background ........................................................................................ 40

1.6 Interrupt Flag Conformance per State ............................................................................................................ 42

1.6.1 Module Flag Conformance per State ........................................................................................................... 42

1.6.2 Lane-Specific Flag Conformance per State .......................................................................................... 43

1.7 Module Memory Map ......................................................................................................................................................... 44

1.7.1 Register default values ................................................................................................................................... 46

1.7.2 Lower Page 00h ........................................................................................................................................................ 46

1.7.3 Upper Page 00h ........................................................................................................................................................ 56

1.7.4 Upper Page 01h ........................................................................................................................................................ 62

1.7.5 Upper Page 02h ........................................................................................................................................................ 74

1.7.6 Upper Page 10h ........................................................................................................................................................ 79

1.7.7 Upper Page 11h ........................................................................................................................................................ 97

2 Appendix A – Form Factor Signal Names ............................................. 115

3 Appendix B – Host-Module Initialization Example Flows ............................. 115

3.1 Software Init Mode (INITMODE=1) Default................................................................................................... 116

3.2 Module power-down sequence example .............................................................................................................. 119

4 Appendix C – Media advertising codes .............................................. 122

Common management specification Rev 3.0

Table 1- Passive copper cable assembly state behaviors................................. 18

Table 2- Active module state behaviors................................................. 19

Table 3- Module State Changed flag behaviors........................................... 20

Table 4- Module Application Advertising format for one application..................... 27

Table 5- 400GBASE-DR4 Application Advertising Example.................................. 29

Table 6- 400G-SR8 Transceiver Application Advertising Example.......................... 30

Table 7- 8x50G AOC Application Advertising Example..................................... 31

Table 8- Data path state behaviors for active modules.................................. 33

Table 9- Data Path State Change flag behaviors for active modules...................... 34

Table 10- Control field dependency on Explicit Control bit............................. 38

Table 11- Tx Input Eq control relationship to Tx Adaptive Input Eq Enable.............. 40

Table 12- Fixed Tx Input Equalization Codes............................................ 40

Table 13- Rx Output Emphasis Codes..................................................... 41

Table 14- Rx Output Amplitude Codes.................................................... 41

Table 15- Module Flag Conformance...................................................... 42

Table 16- Lane-Specific Flag Conformance............................................... 43

Table 17- Lower Page Overview (Lower Page)............................................. 46

Table 18- Identifier and Status Summary (Lower Page)................................... 47

Table 19- Module State Encodings....................................................... 47

Table 20- Lane Flag Summary (Lower Page)............................................... 47

Table 21- Module Flags (Lower Page, active modules only).............................. 49

Table 22- Module Monitors (Lower Page, active modules only)............................ 50

Table 23- Module Global and Squelch Mode Controls (Lower Page, active modules only).... 51

Table 24- Module Level Flag Masks (Lower Page, active modules only).................... 51

Table 25- Byte 85 Module Type Encodings................................................ 53

Table 26- Application Advertising Fields (Lower page).................................. 53

Table 27- Upper Page 00 Overview (Page 00h)............................................ 56

Table 28- Identifiers (Page 00h)....................................................... 57

Table 29- Date Code (Page 00h)......................................................... 58

Table 30- Module Power Class and Max Power (Page 00h).................................. 59

Table 31- Cable Assembly Length (Page 00h)............................................. 59

Table 32- Media Connector Type (Page 00h).............................................. 59

Table 33- Copper Cable Attenuation (Page 00h).......................................... 60

Table 34- Media lane interface implementation (Page 00h)............................... 60

Table 35- Far end cable lane groups advertising codes (Page 00h)....................... 61

Table 36- Media Interface Technology encodings......................................... 62

Table 37- Upper Page 01 Overview (Page 01h)............................................ 62

Table 38- Module Firmware and Hardware Revisions (Page 01h)............................ 63

Table 39- Supported Fiber Link Length (Page 01h)....................................... 64

Table 40- Implemented Management Interface Features Advertising (Page 01h)............. 65

Table 41- State Duration Encoding (Page 01h)........................................... 66

Table 42- Module Characteristics Advertising (Page 01h)................................ 67

Table 43- Implemented Controls Advertisement (Page 01h)................................ 68

Table 44- Implemented Flags Advertisement (Page 01h)................................... 69

Table 45- Implemented Monitors Advertisement (Page 01h)................................ 69

Table 46- Implemented Signal Integrity Controls (Page 01h)............................. 71

Table 47- Media Lane Assignment Advertising (Page 01h)................................. 72

Table 48- Additional Application Advertising Fields (Page 01h)......................... 72

Table 49- Upper Page 02 Overview (Page 02h)............................................ 74

Table 50- Module-Level Monitor Thresholds (Page 02h)................................... 76

Table 51- Lane-specific Monitor Thresholds (Page 02h, active modules only)............. 78

Table 52- Upper Page 16 Overview (Page 10h)............................................ 79

Table 53- Data Path Power control (Page 10h, active modules only)...................... 80

Table 54- Lane-specific Control Fields (Page 10h, active modules only)................. 80

Table 55- Staged Control Set 0, Apply Controls (Page 10h, active modules only)......... 83

Table 56- Staged Control Set 0, Application Select Controls (Page 10h, active modules

only).................................................................................. 84

Table 57- Staged Control Set 0, Tx Controls (Page 10h, active modules only)............ 85

Table 58- Staged Control Set 0, Rx Controls (Page 10h, active modules only)............ 86

Common management specification Rev 3.0

Table 59- Staged Control Set 1, Apply Controls (Page 10h, active modules only)......... 88

Table 60- Staged Control Set 1, Application Select Controls (Page 10h, active modules

only).................................................................................. 89

Table 61- Staged Control Set 1, Tx Controls (Page 10h, active modules only)............ 90

Table 62- Staged Control Set 1, Rx Controls (Page 10h, active modules only)............ 91

Table 63- Lane-Specific Flag Masks (Page 10h, active modules only)..................... 93

Table 64- Upper Page 17 Overview (Page 11h)............................................ 97

Table 65- Data Path State Indicator, per lane (Page 11h) (see Table 66)................ 98

Table 66- Data Path State Indicator Encodings.......................................... 98

Table 67- Lane-Specific State Changed Flags (Page 11h)................................. 98

Table 68- Lane-Specific TX Flags (Page 11h)............................................ 99

Table 69- RX Flags (Page 11h, active modules only).................................... 101

Table 70- Lane-Specific Monitors (Page 11h, active modules only)...................... 102

Table 71- Configuration Error Code registers (Page 11h, active modules only).......... 104

Table 72- Configuration Error Codes (Page 11h, active modules only)................... 104

Table 73- Indicators for Active Control Set, Application Selected (Page 11h, active

modules only)......................................................................... 105

Table 74- Indicators for Active Control Set, Tx Controls (Page 11h, active modules only)

...................................................................................... 106

Table 75- Indicators for Active Control Set, Rx Controls (Page 11h, active modules only)

...................................................................................... 107

Table 76- Module Media Lane to Module Media Wavelength and Fiber mapping (Page 11h,

active modules only).................................................................. 109

Table 77- Form Factor Signal Name Associations........................................ 115

Table 78- Module Host Electrical Interfaces Codes..................................... 122

Table 79- 850 nm MM media interface advertising codes................................. 124

Table 80- SM media interface advertising codes....................................... 125

Table 81- Passive Copper Cable interface advertising codes........................... 127

Table 82- Active Cable assembly media interface advertising codes..................... 127

Table 83- Base-T media interface advertising codes.................................... 127

Figure 1: Module Current Address Read Operation........................................ 10

Figure 2: Module Random Read........................................................... 11

Figure 3: Sequential Address Read Starting at Module Current Address................... 12

Figure 4: Sequential Address Read Starting with Random Module Read..................... 13

Figure 5: Module Write Byte Operation.................................................. 14

Figure 6: Module Sequential Write Operation............................................ 16

Figure 7: Module State Machine......................................................... 17

Figure 8: Lane Assignment Example...................................................... 26

Figure 9: Data Path State Machine...................................................... 32

Figure 10: Control Set Data Flow Diagram............................................... 39

Figure 11: CMIS Module Memory Map...................................................... 45

1 Management Interface

1.1 Introduction

This specification defines the Common Management Interface Specification (CMIS) for QSFP-

DD, OSFP and COBO in order to enable flexible use of modules and cable assemblies

(hereafter referred to as modules unless cable assemblies are specifically mentioned) by

the user. It shares some similarities with the management interfaces used in other form

factors such as QSFP, SFP, and CFP. This specification supports a module with 8 host

electrical lanes. Support for modules with more host lanes is possible (in increments of

up to 8 lanes) by a bank selection feature (which allows several instances of an

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