Verilog Operator Name Functional Group
[ ] bit-select or part-select
( ) parenthesis
!
~
&
|
~&
~|
^
~^ or ^~
logical negation
negation
reduction AND
reduction OR
reduction NAND
reduction NOR
reduction XOR
reduction XNOR
logical
bit-wise
reduction
reduction
reduction
reduction
reduction
reduction
+
-
unary (sign) plus
unary (sign) minus
arithmetic
arithmetic
{ } concatenation concatenation
{{ }} replication replication
*
/
%
multiply
divide
modulus
arithmetic
arithmetic
arithmetic
+
-
binary plus
binary minus
arithmetic
arithmetic
<<
>>
shift left
shift right
shift
shift
>
>=
<
<=
greater than
greater than or equal to
less than
less than or equal to
relational
relational
relational
relational
==
!=
case equality
case inequality
equality
equality
&
^
|
bit-wise AND
bit-wise XOR
bit-wise OR
bit-wise
bit-wise
bit-wise
&&
||
logical AND
logical OR
logical
logical
?: conditional conditional
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