DSP的EMIF接口使用手册_16bit-NANDFLASH

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Application Report

SPRA433B - December 2001

TMS320C6000 EMIF-to-External SDRAM Interface

Kyle Castille Digital Signal Processing Solutions

ABSTRACT

Interfacing external SDRAM to the Texas Instruments TMS320C6000 digital signal

processor (DSP) is simple, compared to previous generations of TI DSPs, because of the

advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of

external memory devices.

This application report describes the EMIF’s control registers and SDRAM signals along with

SDRAM functionality, including functions supported by the EMIF and performance

considerations when used with the EMIF.

General examples include several SDRAM configurations supported by the EMIF, including

timing analysis. In addition, specific examples are provided using Micron SDRAM.

Contents

1 Interface of C6000 EMIF With SDRAM 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 C620x/C670x Compatible Memory Types 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 C621x/C671x Compatible Memory Types 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 C64x Compatible Memory Types 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 C6000 EMIF-to-SDRAM Physical Interface 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Overview of the C6000 EMIF 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 C620x/C670x SDRAM Interface Summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 C6211/C6711 SDRAM Interface Summary 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 C64x SDRAM Interface Summary 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 C6000 EMIF Signal Descriptions 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 C6211/C6711 Byte-Lane Alignment 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 C64x Byte-Lane Alignment 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 C6211/C6711/C64x Clocking 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 C6000 Clock-to-Output Relationship 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 C6000 EMIF Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 EMIF Global Control Register 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 CE Space Control Registers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 SDRAM Control Register (SDCTL) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 SDRAM Timing Register (SDTIM) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5 C6211/C6711/C64x SDRAM Extension Register (SDEXT) 29. . . . . . . . . . . . . . . . . . . . . .

2.6 Interchangeable SDRAM Devices and Upgrading (C64x only) 30. . . . . . . . . . . . . . . . . . . . . . . . .

TMS320C6000 is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

SPRA433B

TMS320C6000 EMIF-to-External SDRAM Interface

3 SDRAM 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 SDRAM Commands 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Timing Requirements 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 Deactivation (DCAB and DEAC) 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Activate (ACTV) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 SDRAM Read (READ) 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 SDRAM Write (WRT) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.6 Mode Register Set (MRS) 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.7 Refresh 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 SDRAM Initialization 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Monitoring Page Boundaries 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 C620x/C670x Page Boundaries 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 C6211/C6711 Page Boundaries 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 C64x Page Boundaries 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Address Shift 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Timing Constraints 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 C6000 Outputs (ED, EA, CE, BE, SDCAS, SDRAS, SDWE) 52. . . . . . . . . . . . . . . . . . . .

3.5.2 C6000 Inputs (Output Data From the SDRAM, Read ED) 53. . . . . . . . . . . . . . . . . . . . . . .

3.5.3 Timing Comparisons for Four SDRAMs 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Complete Example Using C6201B and Micron’s MT48LC4M16A2-10 55. . . . . . . . . . . . . . . . . . . .

4.1 Register Configuration for C6201B to MT48LC4M16A2 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 EMIF Global Control Registers for C6201B to MT48LC4M16A2 56. . . . . . . . . . . . . . . . .

4.1.2 EMIF CE2 Space Control Register for C6201B to MT48LC4M16A2 56. . . . . . . . . . . . . .

4.1.3 EMIF SDRAM Control Register for C6201B to MT48LC4M16A2 57. . . . . . . . . . . . . . . . .

4.1.4 EMIF SDRAM Refresh Period for C6201B to MT48LC4M16A2 58. . . . . . . . . . . . . . . . . .

5 Complete Example Using C6211 and Micron’s MT48LC16M8A2-8 58. . . . . . . . . . . . . . . . . . . . . . .

5.1 Register Configuration for C6211 to MT48LC16M8A2 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 EMIF Global Control Registers for C6211 to MT48LC16M8A2 59. . . . . . . . . . . . . . . . . .

5.1.2 EMIF CE3 Space Control Register for C6211 to MT48LC16M8A2 59. . . . . . . . . . . . . . .

5.1.3 EMIF SDRAM Control Register for C6211 to MT48LC16M8A2 60. . . . . . . . . . . . . . . . . .

5.1.4 EMIF SDRAM Refresh Period for C6211 to MT48LC16M8A2 60. . . . . . . . . . . . . . . . . . .

5.1.5 EMIF SDRAM Extension Register for C6211 to MT48LC16M8A2 61. . . . . . . . . . . . . . . .

6 Complete Examples Using C6414 and Micron’s MT48LC4M32B2-7 61. . . . . . . . . . . . . . . . . . . . .

6.1 Register Configuration for C6414 to MT48LC4M32B2 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 EMIF Global Control Register for C6414 to MT48LC4M32B2 62. . . . . . . . . . . . . . . . . . .

6.1.2 EMIF CE2 Space Control Register for C6414 to MT48LC4M32B2 62. . . . . . . . . . . . . . .

6.1.3 EMIF SDRAM Control Register for C6414 to MT48LC4M32B2 63. . . . . . . . . . . . . . . . . .

6.1.4 EMIF SDRAM Refresh Period for C6414 to MT48LC4M32B2 63. . . . . . . . . . . . . . . . . . .

6.1.5 EMIF SDRAM Extension Register for C6414 to MT48LC4M32B2 64. . . . . . . . . . . . . . . .

7 References 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Code Example for C6201B to Micron MT48LC4M16A2-10 66. . . . . . . . . . . . . . . . . . . . . .

Appendix B Code Example for C6211 to Micron MT48LC16M8A2-8 68. . . . . . . . . . . . . . . . . . . . . . . .

SPRA433B

TMS320C6000 EMIF-to-External SDRAM Interface

List of Figures

Figure 1. C6000 EMIF-to-16M-Bit SDRAM Interface Using Two 16-Bit-Wide Chips 10. . . . . . . . . . . . . . .

Figure 2. C6000 EMIF-to-16M-Bit SDRAM Interface Using Four 8-Bit-Wide Chips 11. . . . . . . . . . . . . . . .

Figure 3. C6000 EMIF1-to-64M-Bit SDRAM Interface Using Two 16-Bit-Wide Chips 12. . . . . . . . . . . . . .

Figure 4. C6000 EMIF-to-64M-Bit SDRAM Interface Using One 32-Bit-Wide Chip 13. . . . . . . . . . . . . . . .

Figure 5. C6211/C6711 EMIF-to-64M-Bit SDRAM Interface Using One 16-Bit-Wide Chip (Big Endian) 13. . .

Figure 6. C64x EMIFA-to64M-Bit SDRAM Interface Using Two 32-Bit-Wide Chips 14. . . . . . . . . . . . . . . .

Figure 7. C64x EMIFA-to-512M-Bit SDRAM Interface Using One 64-bit-Wide Chip 14. . . . . . . . . . . . . . .

Figure 8. C6201/C6701 EMIF Block Diagram 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 9. C6202/C6203/C6204/C6205 EMIF Block Diagram 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 10. C6211/C6711 EMIF Block Diagram 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 11. C64x EMIF Block Diagram 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 12. C6211/C6711 Byte-Lane Alignment vs. Endianness 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 13. EMIFA (64-bit bus) Byte Alignment by Endianness 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 14. EMIFB (16-bit Bus) Byte Alignment by Endianness 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 15. C6201/C6202/C6203/C6204/C6205 vs. C6201B/C6701 Output Timing 23. . . . . . . . . . . . . . . .

Figure 16. C6211/C6711/C64x Output Timing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 17. C62x/C7x EMIF Global Control Register Diagram 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 18. C64x EMIF Global Control Register Diagram 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 19. C620x/C670x EMIF CE Space Control Register Diagram 26. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 20. C6211/C6711/C64x EMIF CE Space Control Register Diagram 26. . . . . . . . . . . . . . . . . . . . . .

Figure 21. EMIF SDRAM Control Register 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 22. EMIF SDRAM Timing Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 23. C6211/C6711/C64x SDRAM Extension Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 24. SDRAM Logical Address Bits 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 25. Modified Type 2 Logical Address Bits 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26. EMIFA to SDRAM Pin Interface for x16-Bit SDRAM 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 27. EMIFB to SDRAM Pin Interface for x32 Bit SDRAM 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 28. SDRAM DCAB—Closes All Banks in a CE Space 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 29. C6211/C6711/C64x SDRAM DEAC—Closes Single Bank Specified by BS 36. . . . . . . . . . . . .

Figure 30. C620x/C670x SDRAM Read—CAS Latency 3 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31. C6211/C6711 SDRAM Read—CAS Latency 3 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 32. C6211/C6711 SDRAM Read With DEAC 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 33. C64x SDRAM Read—CAS Latency 3 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 34. C620x/C670x SDRAM Burst Length 1 Write 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 35. C6211/C6711 SDRAM Burst Length 4 Write 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 36. C64x SDRAM Burst Length 4 Write 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 37. SDRAM Mode Register Set: MRS Command 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 38. SDRAM Refresh 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 39. Logical Address Breakdown for 1 Bank Bit, 11 Row Bits, 8 Column Bits 47. . . . . . . . . . . . . . .

SPRA433B

TMS320C6000 EMIF-to-External SDRAM Interface

Figure 40. Logical Address Breakdown for 2 Banks, 11 Row Bits, 9 Column Bits 48. . . . . . . . . . . . . . . . .

Figure 41. Outputs From C620x/C670x (Write Data [ED], Control, and Address Signals) 52. . . . . . . . . .

Figure 42. Outputs From C6211/C6711/C64x (Write Data [ED], Control, and Address Signals) 53. . . . .

Figure 43. Input to C6000 (Read Data) 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 44. EMIF Global Control Register Diagram for C6201B to MT48LC4M16A2 56. . . . . . . . . . . . . . .

Figure 45. EMIF CE2 Space Control Register Diagram for C6201B to MT48LC4M16A2 57. . . . . . . . . . .

Figure 46. EMIF SDRAM Control Register for C6201B to MT48LC4M16A2 57. . . . . . . . . . . . . . . . . . . . . .

Figure 47. EMIF SDRAM Refresh Period for C6201B to MT48LC4M16A2 58. . . . . . . . . . . . . . . . . . . . . . .

Figure 48. EMIF Global Control Register Diagram for C6211 to MT48LC16M8A2 59. . . . . . . . . . . . . . . .

Figure 49. EMIF CE3 Space Control Register Diagram for C6211 to MT48LC16M8A2 59. . . . . . . . . . . .

Figure 50. EMIF SDRAM Control Register for C6211 to MT48LC16M8A2 60. . . . . . . . . . . . . . . . . . . . . . .

Figure 51. EMIF SDRAM Refresh Period for C6211 to MT48LC16M8A2 60. . . . . . . . . . . . . . . . . . . . . . . .

Figure 52. EMIF Global Control Register Diagram for C6414 MT48LC4M32B2 62. . . . . . . . . . . . . . . . . . .

Figure 53. EMIF CE2 Space Control Register Diagram 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 54. EMIF SDRAM Control Register for C6414 to MT48LC4M32B2 63. . . . . . . . . . . . . . . . . . . . . . .

Figure 55. EMIF SDRAM Refresh Period for C6414 to MT48LC4M32B2 64. . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table 1. C620x/C670x Compatible Memory Type Characteristics 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2. C621x/C671x Compatible Memory Type Characteristics 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 3. C64x Compatible Memory Type Characteristics 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 4. C6000 EMIF Signal Descriptions: Shared Signals and SDRAM Signals 20. . . . . . . . . . . . . . . . .

Table 5. C6000 EMIF Memory Mapped Registers 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 6. EMIF Global Control Register Bit Field Description 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7. C6000 EMIF CE Space Control Register Bit Field Description for SDRAM 26. . . . . . . . . . . . . . .

Table 8. EMIF SDRAM Control Register Bit Field Description 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 9. EMIF SDRAM Refresh Period Bit Field Description 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 10. C6211/C6711/C64x EMIF SDRAM Extension Register Bit Field Description 29. . . . . . . . . . . .

Table 11. Upgradeable and Compatible SDRAM Devices 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 12. EMIF SDRAM Commands 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 13. Truth Table for SDRAM Commands 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 14. C620x/C670x SDRAM Timing Parameters 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 15. C6211/C6711/C64x SDRAM Timing Parameters 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 16. C6211/C6711/C64x Recommended Values for CMD to CMD Parameters 34. . . . . . . . . . . . . . .

Table 17. Mode Register Value† 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 18. Implied SDRAM Configuration by MRS Value 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 19. C620x/C670x Byte Address to EA Mapping for SDRAM RAS and CAS 49. . . . . . . . . . . . . . . . .

Table 20. C6211/C6711 Byte Address to EA Mapping for SDRAM RAS and CAS 49. . . . . . . . . . . . . . . . .

Table 21. C64x Byte Address to EA Mapping for SDRAM RAS and CAS 50. . . . . . . . . . . . . . . . . . . . . . . .

Table 22. MT48LC4M16A2-10 andC6201B-200 Timing Parameters 54. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPRA433B

TMS320C6000 EMIF-to-External SDRAM Interface

Table 23. MT48LC4M16A2-8 and C6202/C6203/C6204/C6205-250 Timing Parameters 54. . . . . . . . . .

Table 24. MT48LC16M8A2-8 and C6211-150 Timing Parameters 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 25. MT48LC16M8A2-8 and C6211-150 Timing Parameters 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 26. SDRAM Registers 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 27. Timing Parameter Calculation for SDRAM Control Register for C6201B to MT48LC4M16A2 57. . .

Table 28. Period Calculation for SDRAM Refresh Period for C6201B to MT48LC4M16A2 58. . . . . . . . .

Table 29. SDRAM Registers for C6211 to MT48LC16M8A2 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 30. Timing Parameter Calculation for SDRAM Control Register for C6211 to MT48LC16M8A2 60. . .

Table 31. Period Calculation for SDRAM Refresh Period for C6211 to MT48LC16M8A2 60. . . . . . . . . . .

Table 32. SDRAM Extension Register Values for C6211 to MT48LC16M8A2 61. . . . . . . . . . . . . . . . . . . . .

Table 33. SDRAM Registers for C6414 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 34. Global Control Register for C6414 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 35. Timing Parameter Calculation for SDRAM Control Register for C6414 to MT48LC4M32B2 63. . .

Table 36. Period Calculation for SDRAM Refresh Period for C6211 to MT48LC16M8A2 64. . . . . . . . . . .

Table 37. SDRAM Extension Register Values for C6414 to MT48LC4M32B2 64. . . . . . . . . . . . . . . . . . . .

1 Interface of C6000 EMIF With SDRAM

The EMIF of all C6000 devices offer a glueless interface to industry-standard SDRAM in the

most commonly available configurations, including 16M bits x 8, 16M bits x 16, 64M bits x 16,

and 64M bits x 32 devices.

†

Depending on the specific C6000 device, additional configurations

may be supported.

1.1 C620x/C670x Compatible Memory Types

The C620x/C670x EMIF supports a glueless interface to a 16M-bit, 2-bank and a 64M-bit,

4-bank SDRAM, offering system designers an interface to high-speed and high-density memory.

lists the possible SDRAM configurations that are fully supported by the EMIF.

As Table 1 shows, the SDRAM supported by the C620x/C670x EMIF has either eight or nine

column address bits and maps into a memory space equal to or smaller than 16M bytes.

Because the C620x/C670x EMIF has a 32-bit word size, four 8-bit or two 16-bit devices must be

used in parallel to create a 32-bit word.

C6000 is a trademark of Texas Instruments.

†

For a complete list of Texas Instruments DSP devices, go to the TI web site at http://www.ti.com

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