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Proprietary & Confidential
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4 August 2009
GV7601 Aviia™ Receiver Data Sheet
www.gennum.com
Key Features
• Serial digital video receiver for standard and high
definition component video:
• SD 525i and 625i
• HD 720p 24, 25, 30, 50 and 60
• HD 1080i 50, 60
• HD 1080p 24, 25, 30, 50 and 60
• Supports 8-bit, 10-bit or 12-bit component digital
video:
• RGB or YCbCr 4:4:4 sampled
• YCbCr 4:2:2 or 4:2:0 sampled
• Integrated cable equalizer for long reach cable
performance
• 230m typical HD performance over high-quality 75Ω
coaxial cable (Belden 1694A or equivalent)
• 160m typical HD performance over RG59 or
equivalent 75Ω coaxial cable
• Serial digital loop-though output
• Integrated audio de-embedder for the extraction of up
to 8 channels of 48kHz digital audio
• Supports IEC 13818-1 compliant transport streams
over the Asynchronous Serial Interface (ASI)
• Automatic selection between SD/HD component video
and ASI input data
• Ancillary (ANC) data detection and extraction
• User selectable processing features, including:
• Timing Reference Signal (TRS) error detection and
correction
• ANC data checksum error detection and correction
• Programmable ANC data detection
• Line number and CRC error detection and correction
• Illegal video code word re-mapping
• 4-wire Gennum Serial Peripheral Interface (GSPI) for
external host command and control
•JTAG test interface
• 1.2V core and 3.3V analog voltage power supplies
• 1.8V or 3.3V selectable digital I/O power supply
• Small footprint 100-BGA (11mm x 11mm)
• Low power operation, typically 570mW at HD
• Pb-free and RoHS compliant
Applications
• Digital video recorders (DVR)
• Video servers
• Video mixers and switchers
• Image capture devices
• Video framegrabbers
•Camcorders
• Video monitors & displays
Description
The GV7601 is a serial digital video receiver for standard
and high definition component video, operating at
270Mb/s, 1.485Gb/s and 2.97Gb/s data rates. With
integrated cable equalizer technology, the GV7601 is
capable of receiving digital video over 75Ω coaxial cable at
lengths up to 460m for standard definition video, and up to
230m for high definition. This provides a complete receive
solution for the transmission of both interlaced and
progressive component digital video, up to 1920 x 1080, in
coaxial cable-based video systems.
Using the GV7601 with the complete Aviia™ receiver
reference design, it is possible to implement an all-digital,
bi-directional multimedia interface over coax. This
interface allows both DC power and a bi-directional,
half-duplex, auxiliary data interface to be carried over the
same single, robust and cost effective coaxial cable as the
high-speed serial digital video. The GV7601 also provides a
re-timed serial digital output for video loop-through
applications.
The GV7601 includes a broad range of user-selectable
processing features, such as Timing Reference Signal (TRS)
error detection and extraction, illegal code word
re-mapping, and ancillary data packet extraction. The
content of ancillary data packets, embedded by an Aviia
transmitter, can be extracted and retrieved via the host
interface. Device configuration and status reporting is
accomplished via the Gennum Serial Peripheral Interface
(GSPI). Alternatively, many processing features and
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4 August 2009
2 of 147
Proprietary & Confidential
operational modes can be configured directly through
external pin settings.
The device can output both 8-bit, 10-bit and 12-bit video
data, for RGB or YCbCr 4:4:4, and YCbCr 4:2:2 or 4:2:0. A
configurable 20-bit wide parallel digital video output bus is
provided, with associated pixel clock and timing signal
outputs. The GV7601 supports ITU-R BT.656 SD formats,
and HD formats conforming to ITU-R BT.709 and BT.1120-6
for 1125-line formats, and SMPTE 296M for 750-line
formats. The device may also be configured to output
CEA-861 timing.
The GV7601 audio de-embedding function allows the up to
8 channels of serial digital audio within the ancillary data
space of the video data stream to be extracted. The audio
output signal formats supported by the device include
AES/EBU for professional applications, S/PDIF, and I
2
S.
16-bit, 20-bit and 24-bit audio formats are supported at
48kHz synchronous-to-video for SD video formats and
48kHz synchronous or asynchronous for HD formats.
Additional audio processing features include: individual
channel extraction, audio group selection, group
replacement, channel swapping and audio channel status
extraction.
The GV7601 also supports an Asynchronous Serial
Interface (ASI) 270Mb/s input, carrying compressed audio
and video transport streams, conforming to IEC 13818-1.
Transport stream data is output from the device at a
synchronous 27MHz clock rate. The device will
automatically deserialize and 8b/10b decode the data.
Packaged in a space saving 100-BGA, the GV7601 is ideal
for designs where high-density component placement is
required. Typically requiring only 570mW power, the
device can be used as a high bandwidth alternative to
analog composite or component video interfaces, providing
a high quality, all-digital, long reach video receive solution.
Figure A: GV7601 Block Diagram
SDI
SDI
Video/Data
Buffer
Host Interface &
JTAG Test
SDO
SDO_EN
RECLK_EN
MCLK
ACLK
WCLK
AOUT1/2
I/O Control
PCLK
AGC
AGC
SDO
EQ_GND
EQ_VDD
LB_CONT
VBG
LF
XTAL2
XTAL1
XTAL_OUT
656_BYPASS
ASI
AUDIO_EN
PROC_EN
861_EN
20BIT/10BIT
AOUT3/4
AOUT5/6
AOUT7/8
DOUT[19:0]
STAT[5:0]
YANC/CANC
ERROR
RATE_DET[1:0]
F/DE
V/VSYNC
H/HSYNC
LOCKED
Error
Detection,
ANC Data
Extraction
TRS, Line
Number, CRC
and EDH
Insertion
Audio
De-embedder
and
Audio Clock
Generation
ASI Sync Detect,
Word Alignment &
8b/10b Decode
Serial Video
Descrambler,
Word Alignment
& Flywheel
Crystal
Buffer/
Oscillator
Serial to
Parallel
Conversion
Data
Re-timer
Cable
Equalizer
Output
Buffer &
Mux
BUFF_VDD
BUFF_GND
AVDD
AGND (x6)
PLL_VDD (x3)
PLL_GND (x3)
VCO_VDD
VCO_GND
STANDBY
RESET
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
JTAG_EN
CORE_GND (x5)
CORE_VDD (x4)
IO_GND (x4)
IO_VDD (x4)
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4 August 2009
3 of 147
Proprietary & Confidential
Revision History
Contents
Key Features........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
1. Pin Out...............................................................................................................................................................9
1.1 Pin Assignment ..................................................................................................................................9
1.2 Pin Descriptions ................................................................................................................................9
2. Electrical Characteristics ......................................................................................................................... 16
2.1 Absolute Maximum Ratings ....................................................................................................... 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ..................................................................................................... 17
2.4 AC Electrical Characteristics ..................................................................................................... 19
3. Input/Output Circuits ............................................................................................................................... 28
4. Detailed Description.................................................................................................................................. 32
4.1 Functional Overview .................................................................................................................... 32
4.2 Serial Digital Input ........................................................................................................................ 32
4.3 Serial Digital Output ..................................................................................................................... 33
4.4 Serial Digital Reclocker ............................................................................................................... 33
4.4.1 Reclocker PLL Loop Bandwidth.................................................................................... 34
4.5 External Crystal/Reference Clock ...........................................................................................34
4.6 Lock Detect ...................................................................................................................................... 35
4.6.1 Asynchronous Lock.......................................................................................................... 36
4.6.2 Signal Interruption............................................................................................................ 36
Version ECR Date Changes and / or Modifications
4 152345 August 2009 Modified Key Features, Description, Table 2-3,
Table 2-4 and Table 4-1.
3 152159 June 2009 Modified Section 4.11.1.1, Section 4.12,
Section 4.17.4, Section 4.19, and Table 4-33.
Added Figure 4-64.
Changed 6.3 Marking Diagram.
2 151833 May 2009 Re-ordered the DOUT[19:10] & DOUT[9:0] in
Table 1-1 to reflect the pin names.
Changed
Figure 4-41.
1 151651 April 2009 Changed DOUT[18_10] and DOUT[9:0] pin
descriptions.
Changed 4.16.8 Ancillary Data Extraction and
its registers.
0 151484 February 2009 New document.
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4 August 2009
4 of 147
Proprietary & Confidential
4.7 Video Functionality ...................................................................................................................... 37
4.7.1 Standard Definition Video Output Formats ............................................................. 37
4.7.2 High Definition Video Output Formats...................................................................... 40
4.7.3 Descrambling and Word Alignment........................................................................... 51
4.8 Parallel Video Data Outputs DOUT[19:0] and DOUT[9:0] ................................................ 51
4.8.1 Parallel Data Bus Buffers.................................................................................................51
4.8.2 Parallel Output in Video Mode ..................................................................................... 55
4.8.3 Parallel Output in ASI Mode.......................................................................................... 55
4.8.4 Parallel Output In Data-Through Mode..................................................................... 56
4.8.5 Parallel Output Clock (PCLK)......................................................................................... 56
4.8.6 DDR Parallel Clock Timing............................................................................................. 57
4.9 Timing Signal Generator ............................................................................................................. 58
4.10 Programmable Multi-function Outputs ............................................................................... 59
4.11 H:V:F Timing Signal Generation ............................................................................................60
4.11.1 CEA-861 Timing Generation ....................................................................................... 62
4.12 Automatic Video Standards Detection ................................................................................ 73
4.13 EDH Detection .............................................................................................................................. 75
4.13.1 EDH Packet Detection ................................................................................................... 76
4.13.2 EDH Flag Detection ........................................................................................................ 76
4.14 Video Signal Error Detection & Indication ......................................................................... 77
4.14.1 TRS Error Detection........................................................................................................ 78
4.14.2 Line Based CRC Error Detection ................................................................................ 78
4.14.3 EDH CRC Error Detection............................................................................................. 79
4.14.4 HD Line Number Error Detection.............................................................................. 79
4.15 Ancillary Data Detection & Indication ................................................................................. 79
4.15.1 Programmable Ancillary Data Detection................................................................ 82
4.15.2 Ancillary Data Checksum Error................................................................................. 82
4.16 Video Error Correction .............................................................................................................. 83
4.16.1 TRS Correction & Insertion........................................................................................... 84
4.16.2 Line Based CRC Correction & Insertion ................................................................... 84
4.16.3 Line Number Error Correction & Insertion............................................................. 85
4.16.4 Ancillary Data Checksum Error Correction & Insertion .................................... 85
4.16.5 EDH CRC Correction & Insertion ............................................................................... 85
4.16.6 Illegal Word Remapping............................................................................................... 85
4.16.7 TRS and Ancillary Data Preamble Remapping...................................................... 86
4.16.8 Ancillary Data Extraction............................................................................................. 86
4.17 Audio De-embedder ................................................................................................................... 91
4.17.1 Serial Audio Data I/O Signals...................................................................................... 91
4.17.2 Serial Audio Data Format Support ............................................................................ 93
4.17.3 Audio Processing............................................................................................................. 97
4.17.4 Error Reporting ..............................................................................................................101
4.18 Gennum Serial Peripheral Interface ...................................................................................102
4.18.1 Command Word Description....................................................................................102
4.18.2 Data Read or Write Access.........................................................................................103
4.18.3 GSPI Timing.....................................................................................................................104
GV7601 Aviia™ Receiver
Data Sheet
52155 - 4 August 2009
5 of 147
Proprietary & Confidential
4.19 Host Interface Register Maps ................................................................................................106
4.19.1 Video Core Registers....................................................................................................106
4.19.2 SD Audio Core................................................................................................................113
4.19.3 HD Audio Core Registers............................................................................................125
4.20 JTAG Test Operation ................................................................................................................137
4.21 Device Power-up .......................................................................................................................139
4.22 Device Reset ................................................................................................................................139
4.23 Standby Mode ............................................................................................................................139
5. References & Relevant Standards.......................................................................................................140
6. Package & Ordering Information ........................................................................................................141
6.1 Package Dimensions ...................................................................................................................141
6.2 Packaging Data .............................................................................................................................142
6.3 Marking Diagram .........................................................................................................................142
6.4 Solder Reflow Profiles ................................................................................................................143
6.5 Ordering Information .................................................................................................................143
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