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MT7621 PROGRAMMING GUIDE
1. MIPS 1004Kc Processor
1.1 Features
8-9-stage pipeline
32-bit Address Paths
64-bit Data Paths to Caches
MIPS32 Enhanced Architecture (Release 2) Features
– Standardized Instruction Set Architecture
– Vectored interrupts and support for an external interrupt controller
– Programmable exception vector base
– Atomic interrupt enable/disable
– Bit field manipulation instructions
MIPS16e Application Specific Extension
– 16 bit encodings of 32-bit instructions to improve code density
– Special PC-relative instructions for efficient loading of addresses and constants
– Data type conversion instructions (ZEB, SEB, ZEH, SEH)
– Compact jumps (JRC, JALRC)
– Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE)
MIPS MT Application Specific Extension (ASE)
– Support for 2 Virtual Processing Elements (VPEs) per CORE
– One Thread Context (TC) per VPE
Programmable L1 Cache Sizes
– Individually configurable instruction and data caches
– 32KB I/D cache
– 4-way set associative
– Up to 9 non-blocking loads
– Data cache supports coherent and non-coherent Write-back with write-allocation
– 32-byte cache line size, doubleword sectored - suitable for standard single-port SRAM
– Cache line locking support
– Non-blocking prefetches
– Duplicate tag array in D-cache allows coherence requests to access the cache in parallel with normal
load/store traffic
Standard Memory Management Unit
– 32 dual-entry MIPS32-style JTLB per VPE with variable page sizes
– JTLBs are sharable under software control
– 4-5 entry instruction TLB
– 8-entry data TLB
OCP Bus Interface Unit (BIU)
– 32b address and 64b data
– Supports bursts of 4x64b
– 8 entry write buffer - handles eviction data, intervention response, uncached, and uncached
accelerated store data
– Simple Byte enable mode allows easier bridging to other bus standards
– Extensions for management of front side L2 cache
– Intervention port supports memory coherency for use in a 1004K Coherent Processing System
Multiply-Divide Unit
– Maximum issue rate of one 32x32 multiply per clock
– Early-in divide control. Minimum 11, maximum 34 clock latency on divide
Power Control
– No minimum frequency
– Support for software-controlled clock divider
– Support for extensive use of fine-grain clock gating
MEDIATEK CONFIDENTIAL
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