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JEDEC Standard No. 21C
Page 4.20.26-1
Release 25A Revision 1.10
4.20.26 - 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/
PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification
DDR4 SDRAM UDIMM Design Specification
Revision 1.10
August 2015
Revision 1.10 Release 25A
JEDEC Standard No. 21C
Page 4.20.26-2
Table of Contents
1 Product Description .......................................................................................................... 5
2 Environmental Requirements........................................................................................... 6
3 Connector Pinout and Signal Description....................................................................... 7
4 Power Details ................................................................................................................... 12
4.1 DIMM Voltage Requirements ................................................................................................................12
4.2
Rules for Power-Up Sequence ............................................................................................12
4.3 Feed Through Voltage (VFT).................................................................................................................13
4.4 12 V Power..............................................................................................................................................13
5 Component Details.......................................................................................................... 14
5.1 Component Types and Placement .......................................................................................................17
5.2 Decoupling Guidelines..........................................................................................................................17
6 DIMM Design Details ....................................................................................................... 18
6.1 Signal Groups ........................................................................................................................................18
6.2 Explanation of Net Structure Diagrams ...............................................................................................18
6.3 General Net Structure Routing Rules ..................................................................................................19
6.3.1 Clock, Control, and Address/Command Groups ........................................................... 19
6.3.2 Lead-in vs. Loaded Sections ......................................................................................... 20
6.3.3 Length/Delay Matching to SDRAM Devices..................................................................20
6.3.4 Velocity Compensation.................................................................................................. 21
6.3.5 Load/Delay Compensation ............................................................................................21
6.3.6 Data and Strobe Group .................................................................................................21
6.3.7 ALERT_n Wiring............................................................................................................21
6.3.8 Via Compensation .........................................................................................................22
6.3.9 Plane Referencing.........................................................................................................23
6.4 Address Mirroring..................................................................................................................................23
6.5 DIMM Routing Space Constraints ........................................................................................................25
6.6 DIMM Physical Requirements...............................................................................................................26
6.6.1 Via Size .........................................................................................................................26
6.6.2 Component Pad Sizes and Geometry...........................................................................26
6.6.3 DRAM Package Size .....................................................................................................26
6.6.4 Clock Termination .........................................................................................................26
6.6.5 DQ Stub Resistor ..........................................................................................................26
6.6.6 ZQ Calibration Wiring ....................................................................................................26
6.6.7 TEN Wiring ....................................................................................................................26
6.7 Reference Stackups...............................................................................................................................27
6.8 Impedance Targets ................................................................................................................................29
6.9 SPD-TSE Wiring and Placement...........................................................................................................30
6.10 DQ Mapping to Support CRC................................................................................................................31
7 Serial Presence Detect.................................................................................................... 34
7.1 Serial Presence Detect Definition.........................................................................................................34
8 Product Label................................................................................................................... 37
8.1 DDR4 DIMM Label Format for DRAM-only module types...................................................................37
8.2 DDR4 DIMM Label Format for Hybrid module types...........................................................................41
9 JEDEC Process................................................................................................................ 44
JEDEC Standard No. 21C
Page 4.20.26-3
Release 25A Revision 1.10
List of Tables
Table 1 — Product Family Attributes............................................................................................................ 5
Table 2 — Environmental Parameters .......................................................................................................... 6
Table 3 — Pin Definition ................................................................................................................................ 7
Table 4 — Input/Output Functional Description .......................................................................................... 8
Table 5 — DDR4 288 Pin UDIMM Pin Wiring Assignments....................................................................... 10
Table 6 — DDR4 UDIMM DC Operating Voltage - 1.2 V operation ........................................................... 12
Table 7 — DDR4 x8 SDRAM DIMM Pad Array ............................................................................................ 15
Table 8 — DDR4 x16 SDRAM DIMM Pad Array .......................................................................................... 16
Table 9 — UDIMM Decoupling Capacitor Guidelines................................................................................ 17
Table 10 — CK, CTRL, and ADD/CMD Group Length Matching Rules .................................................... 19
Table 11 — Data and Strobe Group Length Matching Rules.................................................................... 21
Table 12 — Plane Referencing .................................................................................................................... 23
Table 13 — DIMM Wiring Definition for Address Mirroring ...................................................................... 24
Table 14 — Routing Space Constraints ..................................................................................................... 25
Table 15 — Preferred 10 Layer Stackup for UDIMMs ................................................................................27
Table 16 — Preferred 8 Layer Stackup for UDIMMs .................................................................................. 28
Table 17 — Preferred 6 Layer Stackup for UDIMMs .................................................................................. 28
Table 18 — Impedance Assignments by Signal Type............................................................................... 29
Table 19 — SPD DQ Nibble Map for CRC ................................................................................................... 31
Table 20 — Nibble/Byte DQ Map Patterns for CRC ................................................................................... 32
Table 21 — Example of DQ Mapping for CRC............................................................................................ 33
Table 22 — SPD Address Map..................................................................................................................... 34
Table 23 — SPD Block 0: Base Configuration and DRAM Parameters ................................................... 34
Table 24 — Preproduction Registration Table........................................................................................... 39
Revision 1.10 Release 25A
JEDEC Standard No. 21C
Page 4.20.26-4
List of Figures
Figure 1 — Graphical View of Recommended Power Sequence ............................................................. 13
Figure 2 — Graphical View of Recommended Power Down Sequence................................................... 13
Figure 3 — DIMM Ball Patterns for DDR4 SDRAM Components.............................................................. 14
Figure 4 — Fly-By Topology ........................................................................................................................ 18
Figure 5 — Net Structure Example.............................................................................................................. 19
Figure 6 — Example Address Routing Topology ...................................................................................... 20
Figure 7 — ALERT_n Wiring........................................................................................................................ 22
Figure 8 — Via Compensation Diagram ..................................................................................................... 22
Figure 9 — Block Diagram: SPD-TSE / SPD............................................................................................... 30
Figure 10 — Example of DQ Wiring with Mapping for CRC...................................................................... 33
JEDEC Standard No. 21C
Page 4.20.26-5
Release 25A Revision 1.10
1 Product Description
This specification defines the electrical and mechanical requirements for 288-pin, 1.2 V (VDD), Unbuffered,
Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These
DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs.
Reference design examples are included which provide an initial basis for DDR4 UDIMM designs.
Modifications to these reference designs may be required to meet all system timing, signal integrity, and
thermal requirements for PC4-1600, PC4-1866, PC4-2133, PC4-2400, PC4-2666, and PC4-3200 support. All
DDR4 UDIMM implementations must use simulations and lab verification to ensure proper timing
requirements and signal integrity in the design.
This specification follows the JEDEC standard DDR4 component specification (refer to JEDEC standard
JESD79-4, at www.jedec.org).
Table 1 — Product Family Attributes
DIMM Organization x64, x72 ECC Notes
DIMM Dimensions
(nominal)
133.35 mm x 31.25 mm Refer to MO-309
Pin Count 288
DDR4 SDRAMs Sup-
ported
4 Gb, 8 Gb, 12 Gb, 16 Gb, 32 Gb
78/106-ball FBGA package for x8 and 96/112-ball FBGA for
x16 devices.
Refer to MO-207:
x8 variations DT-z, DW-z
x16 variations DU-z, DY-z
Capacity 2 GB - 64 GB
DDR4 SDRAM width x8, x16
Serial Presence Detect,
Thermal Sensor (SPD-
TSE/SPD)
512 byte TSE2004av and EE1004-v specifications
Voltage Options
PC4 - 1.2 V VDD
VDDSPD: 2.5 V or 3.3 V ± 10%
The VDDSPD supply has VSS as its return path. VDDSPD is
separate from the VPP power supply.
2.5 V VPP
This supply has VSS as its return path. It is a separate supply
from VDDSPD.
12 V May be available on the connector but not used by UDIMMs
Interface 1.2 V signaling
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