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CoreSight Architecture Specification.pdf
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CoreSight Architecture Specification 详细说明
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Copyright © 2004, 2005 ARM Limited. All rights reserved.
ARM IHI 0029B
CoreSight
™
v1.0
Architecture Specification
ii Copyright © 2004, 2005 ARM Limited. All rights reserved. ARM IHI 0029B
CoreSight
Architecture Specification
Copyright © 2004, 2005 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks owned by ARM Limited. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
29 September 2004. A First release.
24 March 2005. B Second draft. Editorial changes and clarifications.
ARM IHI 0029B Copyright © 2004, 2005 ARM Limited. All rights reserved. iii
Contents
Preface
About this specification ................................................................................. xii
Feedback ................................................................................................... xviii
Part A CoreSight Architecture
Chapter 1 Introduction
1.1 About the CoreSight architecture ................................................................ 1-2
1.2 Structure of the CoreSight architecture ....................................................... 1-4
1.3 CoreSight component types ........................................................................ 1-6
1.4 CoreSight topology detection ...................................................................... 1-8
1.5 Component access using memory mapped interfaces instead of JTAG .. 1-10
Part B CoreSight Visible Component Architecture
Chapter 2 Visible Component Architecture
2.1 About the visible component architecture ................................................... 2-2
Chapter 3 CoreSight Programmer’s Model
3.1 About the programmer’s model ................................................................... 3-2
Contents
iv Copyright © 2004, 2005 ARM Limited. All rights reserved. ARM IHI 0029B
3.2 Reserved locations ..................................................................................... 3-6
3.3 Component identification registers ............................................................. 3-7
3.4 Peripheral identification registers ............................................................... 3-8
3.5 Class 0x1 ROM table ................................................................................ 3-10
3.6 Class 0x9 CoreSight component .............................................................. 3-11
3.7 Class 0xF PrimeCell or system component .............................................. 3-23
3.8 Spanning multiple 4KB blocks .................................................................. 3-24
Chapter 4 Topology Detection Registers
4.1 About topology detection registers ............................................................. 4-2
4.2 Requirements for topology detection signals .............................................. 4-3
4.3 Combination with integration registers ....................................................... 4-4
4.4 Interfaces that are not connected or implemented ..................................... 4-5
4.5 Variant interfaces ........................................................................................ 4-6
4.6 Documentation requirements for topology detection registers ................... 4-8
Part C CoreSight Reusable Component Architecture
Chapter 5 Reusable Component Architecture
5.1 About the reusable component architecture ............................................... 5-2
Chapter 6 AMBA 3 APB Interface
6.1 About the AMBA 3 APB interface ............................................................... 6-2
6.2 AMBA 3 APB interface signals ................................................................... 6-3
6.3 AMBA 3 APB interface width ...................................................................... 6-5
6.4 Use of PADDRDBG[31] .............................................................................. 6-6
6.5 Alternative views of the register file ............................................................ 6-7
Chapter 7 AMBA 3 ATB Interface
7.1 About the AMBA 3 ATB interface ............................................................... 7-2
7.2 AMBA documentation ................................................................................. 7-3
7.3 AMBA 3 ATB interface Signals ................................................................... 7-4
7.4 AMBA 3 ATB interface rules ....................................................................... 7-5
7.5 ATVALID and ATREADY ............................................................................ 7-7
7.6 ATID ........................................................................................................... 7-8
7.7 AFVALID and AFREADY ............................................................................ 7-9
7.8 AMBA 3 ATB interface signal naming conventions .................................. 7-12
7.9 AMBA 3 ATB interface timing parameters ................................................ 7-13
Chapter 8 Channel Interface
8.1 About the channel interface ........................................................................ 8-2
8.2 Channels .................................................................................................... 8-4
8.3 Channel interface signals ........................................................................... 8-5
8.4 Channel connections .................................................................................. 8-6
8.5 Synchronous and asynchronous conversions ............................................ 8-7
Contents
ARM IHI 0029B Copyright © 2004, 2005 ARM Limited. All rights reserved. v
Chapter 9 Authentication Interface
9.1 About the authentication interface .............................................................. 9-2
9.2 Definitions of secure and invasive debug .................................................... 9-3
9.3 Authentication interface signals .................................................................. 9-4
9.4 Authentication rules .................................................................................... 9-5
9.5 User mode debugging ................................................................................. 9-8
9.6 Control of the authentication interface ........................................................ 9-9
9.7 Exemptions in the authentication interface ............................................... 9-10
Chapter 10 Topology Detection at the Component Level
10.1 About topology detection at the component level ..................................... 10-2
10.2 Interface types for topology detection ....................................................... 10-3
10.3 Interface requirements for topology detection ........................................... 10-5
10.4 Signals for topology detection ................................................................... 10-7
Part D CoreSight System Architecture
Chapter 11 System Architecture
11.1 About the system architecture .................................................................. 11-2
Chapter 12 System Design
12.1 About system design ................................................................................. 12-2
12.2 Clock and power domains ......................................................................... 12-3
12.3 Control of authentication interfaces .......................................................... 12-5
12.4 Memory system design ............................................................................. 12-6
Chapter 13 Physical Interface
13.1 About the physical interface ...................................................................... 13-2
13.2 Target system connector .......................................................................... 13-3
13.3 Target connector description .................................................................... 13-5
13.4 Decoding requirements for trace capture devices ..................................... 13-9
13.5 Electrical characteristics .......................................................................... 13-10
13.6 Signal details ........................................................................................... 13-12
Chapter 14 Trace Formatter
14.1 About trace formatters .............................................................................. 14-2
14.2 Frame descriptions ................................................................................... 14-3
14.3 Modes of operation ................................................................................... 14-9
14.4 Flush of trace data at the end of operation ............................................. 14-10
Chapter 15 ROM table
15.1 About the ROM table ................................................................................ 15-2
15.2 ROM table format ...................................................................................... 15-3
15.3 ROM hierarchy .......................................................................................... 15-6
15.4 Location of ROM table .............................................................................. 15-8
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