没有合适的资源?快使用搜索试试~ 我知道了~
首页ZCU102开发板原理图
ZCU102开发板原理图
4星 · 超过85%的资源 需积分: 42 195 下载量 98 浏览量
更新于2023-03-16
评论 8
收藏 4.57MB PDF 举报
Xilinx Zynq UltraScale+MPSoC ZCU102原理图,HW-Z1-ZCU102 Evaluation Board (XCZU9EG-FFVB1156)
资源详情
资源评论
资源推荐
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY
DOCUMENTATION.
INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF
CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT
STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF
KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR
XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,
AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN
THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.
YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,
OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,
BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,
OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.
XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF
THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,
TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES
NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR
TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY
DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR
ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE
THE DOCUMENTATION.
THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")
ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH
CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY
DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT
IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.
ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY
APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY
DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL
RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE
("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT
THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
DISCLAIMER:
HW-Z1-ZCU102 Evaluation Board
(XCZU9EG-FFVB1156)
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
BF
09/20/2016:10:26
PCB P/N: 1280868
TEST P/N: TSS0179
SCH P/N: 0381701
ASSY P/N: 0431959
871
Title Page
SCHEM, ROHS COMPLIANT
HW-Z1-ZCU102_REV1_0
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
BF
09/20/2016:10:26
PCB P/N: 1280868
TEST P/N: TSS0179
SCH P/N: 0381701
ASSY P/N: 0431959
872
Block Diagram
SCHEM, ROHS COMPLIANT
HW-Z1-ZCU102_REV1_0
12VDC
Clock devices
Pages 39-41
PS/PL/System
0
HP
BANK# PAGE#
BANK 0
BANK#
PROG. PB
Page 12
Page 22
PAGE#
INIT,DONE LEDs
GTH228
GTH229
44
48
66
49
50
65
PSDDR 504
BANK 66
BANK 65
MGTH128-130
MGTH228-230
U1
PS 503
BANK 64
64
67
47
12
13
7
3
PS 500
BANK 48
BANK 67
PS 501, 502
BANK 49
PWR CONNECTORS
8
7
8
11
6
11
5
XCZU9EGFFVB1156
GTH230
9
10
Page 87
59
DDR4 Comp. Memory
Page 25
MECHANICALSJTAG CONN.
HP
HP
PS DDR
PS PWR
GTH128
GTH129
GTH130
GTR505
502
501
503
500
HP
CONFIG)
PS
PS
PS
504
PS
PS
PS
16-bit: 1 x 16-bit
MT40A256M16GE-075E
BANK 44 4
BANK 47 5
BANK 50 6
PS POR, SRST PBs
(PS-Side
VCCINT @ 40A
VCCBRAM @ 6A
VCCAUX @ 3A
VCC1V2 @ 2A
VADJ_FMC @ 10A
MGTAVCC @ 6A
MGTAVTT @ 6A
PL_DDR4_VPP_2V5 @ 1A
PL DDR4 VTT @ 6A
MGTVCCAUX @ 1A
VCCPSINTFP @ 10A
VCCPSINTLP @ 2A
DDR4_DIMM_VDDDQ @ 6A
VCCOPS @ 4A
UTIL_5V0 @ 10A
UTIL_3V3 @ 20A
PL PMBUS RAILS:
Pages 60-68
Page 66, 69, 85
PL LDOs:
Pags 70-78
PS PMBUS RAILS:
PS_DDR4_VPP_2V5 @ 1A
PS DDR4 VTT @ 6A
VCCPSAUX @ 500mA
VCCPSPLL @ 200mA
MGTRAVCC @ 400mA
MGTRAVTT @ 100mA
VCCOPS3 @ 300mA
VCCPSDDRPLL @ 100mA
Page 72-80, 85
PS LDOs:
UTIL_1V8 @ 1A
UTIL_1V13 @ 1A
Page 83
UTIL LDOs:
Page 83-84
Main PMBUS UTIL RAILS
DDR4 DUAL
72-Bit SODIMM
DDR4 DIMM
DECOUPLING
Page 23 Page 24
MUX connections:
PCIe / DisplayPort
USB3.0 / SATA
Page 43-45, 48, 51
HDMI
SMA
Pages 35-37, 40
FMC HPC1
GT Interface
Pages 30-33
FMC HPC0
LA bus
Pages 41-43
FMC HPC1
LA Bus
Pages 30-33
FMC HPC0
LA Bus
Pages 26-29
FMC HPC0
GT Interface
Pages 26-29
SFP 2x2 Cage
Page 34
PMOD
125MHz CLK
Trace
IIC1 Connection
Pages 54-55, 58
PS UART
PS I2C
PS QSPI
Page 42, 46, 57-58
Prototype Header
Display Port Aux
MSP430 GPIO
IIC0 Connection
Pages 44, 56, 38
HDMI Recovered
Clock
Page 35-37
MGTR 505 14
SI570 Programmable
Oscillator
Page 40
HDMI TX Clock
Pages 35-37
SFP Recovered
Clock
Page 34
GPIO
74.25MHz clk
Page 39
SYSMON IIC
SFP Disables
MSP430/CP2108 UART
HDMI Control
Pages 6, 34
SDIO
PMU GPIO
PS Display Port Aux
Pages 47, 44-45
Ethernet
USB
Page 51-52
GTR Muxes
Pages 48
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
BF
09/20/2016:10:26
PCB P/N: 1280868
TEST P/N: TSS0179
SCH P/N: 0381701
ASSY P/N: 0431959
873
Zynq Bank 0
SCHEM, ROHS COMPLIANT
HW-Z1-ZCU102_REV1_0
1
DNP
DNP
R290
2
SYSMON_VP_R_I2C
GND
SYSMON I2C Address jumpers
GND
SYSMON_VN_R_I2C
POR_OVERRIDE select
Default: 2-3 GND
J12
HDR_1X2
2
1 SYSMON_VP_R
SYSMON_VN_R1
2
HDR_1X2
J13
Zynq Bank 0
SYSMON_DXN
SYSMON_DXP
SYSMON_VP_R
SYSMON_VN_R
GND
1%
4.70K
R94
1
2
GND
1
2
3
HDR_1X3
J85
VCCINT
GND
R397
1.00K
1%
1
2
2
1
DNP
DNP
R291
L16
2
1
FERRITE-600
C902
2
1
0.47UF
10V
SYSMON_AGND
1
2
C1
0.1UF
25V
FPGA_SYSMON_AVCC
FERRITE-600
1
2
L17
GND
R132
20.5K
1%
1
2
R133
20.5K
1%
1
2
VCCAUX
VCCAUX
VCCAUX
SYSMON_AGND
GND
IN OUT
GND
REF3012
SYSMON_AGND
1
2
FERRITE-600
L55
SYSMON_AGND
1
2
3
HDR_1X3
J90
1 2
3
SOT23_3
IC VOLT REF, 1.25V
U64
1
2
C384
10UF
10V
1
2
0.47UF
C492
10V
SYSMON_VREFP
SYSMON_VREF
FPGA_SYSMON_AVCC
2
1
R432
100
1%
2
1
1%
100
R433
SYSMON_VN
SYSMON_VPSYSMON_VP_R
SYSMON_VN_R
1
2 50V
2700PF
C408
SYSMON_VREFP
SYSMON_AGND
SYSMON_DXN
SYSMON_DXPNC
NC
VCCINT_VIN_R_N VCCINT_VIN_R_P
SYSMON_VREF FPGA_SYSMON_AVCC
SYSMON_VN SYSMON_VP
U1
AD15
AD14
W18
W17
T18
T17
V18
U17
U18
V17
VN_V17
VP_U18
VREFN_U17
VREFP_V18
GNDADC_T17
VCCADC_T18
DXN_W17
DXP_W18
POR_OVERRIDE_AD14
PUDC_B_0_AD15
XCZU9FFVB1156
BANK 0
SOC_1156_1MM_IRON
SOC_DA7_FFVB1156_IRONWOOD
C25
0.1UF
25V2
1
70246-1201
J93
11 12
4
109
87
65
3
21
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
BF
09/20/2016:10:26
PCB P/N: 1280868
TEST P/N: TSS0179
SCH P/N: 0381701
ASSY P/N: 0431959
874
Zynq Banks 44
SCHEM, ROHS COMPLIANT
HW-Z1-ZCU102_REV1_0
Zynq Banks 44
VCC3V3
GPIO_DIP_SW7
GPIO_LED_7
GPIO_LED_6
GPIO_LED_5
GPIO_LED_4
GPIO_LED_3
GPIO_LED_2
GPIO_LED_1
GPIO_LED_0
GPIO_SW_S
GPIO_SW_E
GPIO_SW_C
GPIO_SW_N
GPIO_SW_W
CLK_74_25_P
CLK_74_25_N
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW1
GPIO_DIP_SW4
GPIO_DIP_SW0
GPIO_DIP_SW6
GPIO_DIP_SW5
2
1
R430
100
1%
CLK_74_25_P
CLK_74_25_N
U1
AE14
AE15
AG15
AF15
AG13
AG14
AF13
AE13
AJ14
AJ15
AH13
AH14
AL12
AK13
AK14
AK15
AM13
AL13
AP12
AN12
AN13
AM14
AP14
AN14
AF14
AJ13
VCCO_44_AJ13
VCCO_44_AF14
IO_L1P_AD11P_44_AN14
IO_L1N_AD11N_44_AP14
IO_L2P_AD10P_44_AM14
IO_L2N_AD10N_44_AN13
IO_L3P_AD9P_44_AN12
IO_L3N_AD9N_44_AP12
IO_L4P_AD8P_44_AL13
IO_L4N_AD8N_44_AM13
IO_L5P_HDGC_AD7P_44_AK15
IO_L5N_HDGC_AD7N_44_AK14
IO_L6P_HDGC_AD6P_44_AK13
IO_L6N_HDGC_AD6N_44_AL12
IO_L7P_HDGC_AD5P_44_AH14
IO_L7N_HDGC_AD5N_44_AH13
IO_L8P_HDGC_AD4P_44_AJ15
IO_L8N_HDGC_AD4N_44_AJ14
IO_L9P_AD3P_44_AE13
IO_L9N_AD3N_44_AF13
IO_L10P_AD2P_44_AG14
IO_L10N_AD2N_44_AG13
IO_L11P_AD1P_44_AF15
IO_L11N_AD1N_44_AG15
IO_L12P_AD0P_44_AE15
IO_L12N_AD0N_44_AE14
XCZU9FFVB1156
BANK 44
SOC_1156_1MM_IRON
SOC_DA7_FFVB1156_IRONWOOD
1/10W
CPU_RESET
A
B
C
D
1234
D
C
B
A
4 3 2 1
SHEET SIZE: B
SHEET OF
VER:
REV:
DRAWN BY:
TITLE:
DATE: 1.0
01
BF
09/20/2016:10:26
PCB P/N: 1280868
TEST P/N: TSS0179
SCH P/N: 0381701
ASSY P/N: 0431959
875
Zynq Banks 47 48
SCHEM, ROHS COMPLIANT
HW-Z1-ZCU102_REV1_0
Zynq Banks 47 48
PMOD0_0
PMOD0_1
PMOD0_2
PMOD0_3
PMOD0_4
PMOD0_5
PMOD0_6
PMOD0_7
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
PMOD1_4
PMOD1_5
TRACEDATA15
TRACEDATA8
TRACEDATA10
TRACEDATA12
TRACEDATA13
TRACEDATA14
TRACEDATA11
TRACEDATA9
TRACESRST_B
TRACETDO
TRACERTCK
TRACEDBGRQ
TRACETCK
TRACETMS
TRACETDI
TRACETRST_B
TRACEEXTTRIG
TRACEDATA7
TRACEDATA6
TRACEDATA5
TRACEDATA4
TRACEDATA3
TRACECLKA
TRACEDBGACK
VCC3V3
VCC3V3
PMOD1_6
PMOD1_7
TRACEDATA2
TRACEDATA1
TRACECTL
TRACEDATA0
2
1
R431
100
1%
CLK_125_P
CLK_125_N
PL_I2C1_SCL_LS
PL_I2C1_SDA_LS
U1
A20
B20
A22
A21
B21
C21
C22
D21
D20
E20
D22
E22
F20
G20
F21
G21
J20
J19
H21
J21
K19
L19
K20
L20
E21
H20
VCCO_47_H20
VCCO_47_E21
IO_L1P_AD11P_47_L20
IO_L1N_AD11N_47_K20
IO_L2P_AD10P_47_L19
IO_L2N_AD10N_47_K19
IO_L3P_AD9P_47_J21
IO_L3N_AD9N_47_H21
IO_L4P_AD8P_47_J19
IO_L4N_AD8N_47_J20
IO_L5P_HDGC_AD7P_47_G21
IO_L5N_HDGC_AD7N_47_F21
IO_L6P_HDGC_AD6P_47_G20
IO_L6N_HDGC_AD6N_47_F20
IO_L7P_HDGC_AD5P_47_E22
IO_L7N_HDGC_AD5N_47_D22
IO_L8P_HDGC_AD4P_47_E20
IO_L8N_HDGC_AD4N_47_D20
IO_L9P_AD3P_47_D21
IO_L9N_AD3N_47_C22
IO_L10P_AD2P_47_C21
IO_L10N_AD2N_47_B21
IO_L11P_AD1P_47_A21
IO_L11N_AD1N_47_A22
IO_L12P_AD0P_47_B20
IO_L12N_AD0N_47_A20
XCZU9FFVB1156
BANK 47
SOC_1156_1MM_IRON
SOC_DA7_FFVB1156_IRONWOOD
U1
A18
A17
C19
C18
B19
B18
C17
D17
E18
E17
D19
E19
F18
F17
G19
G18
K17
L17
K18
L18
H17
J17
H19
H18
G17
J18
VCCO_48_J18
VCCO_48_G17
IO_L1P_AD15P_48_H18
IO_L1N_AD15N_48_H19
IO_L2P_AD14P_48_J17
IO_L2N_AD14N_48_H17
IO_L3P_AD13P_48_L18
IO_L3N_AD13N_48_K18
IO_L4P_AD12P_48_L17
IO_L4N_AD12N_48_K17
IO_L5P_HDGC_48_G18
IO_L5N_HDGC_48_G19
IO_L6P_HDGC_48_F17
IO_L6N_HDGC_48_F18
IO_L7P_HDGC_48_E19
IO_L7N_HDGC_48_D19
IO_L8P_HDGC_48_E17
IO_L8N_HDGC_48_E18
IO_L9P_AD11P_48_D17
IO_L9N_AD11N_48_C17
IO_L10P_AD10P_48_B18
IO_L10N_AD10N_48_B19
IO_L11P_AD9P_48_C18
IO_L11N_AD9N_48_C19
IO_L12P_AD8P_48_A17
IO_L12N_AD8N_48_A18
XCZU9FFVB1156
BANK 48
SOC_1156_1MM_IRON
SOC_DA7_FFVB1156_IRONWOOD
CLK_125_P
CLK_125_N
1/10W
剩余86页未读,继续阅读
uwocixzwzq
- 粉丝: 0
- 资源: 1
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- RTL8188FU-Linux-v5.7.4.2-36687.20200602.tar(20765).gz
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论1