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The OMAP36xx high-performance, multimedia application device is based on the enhanced OMAP™ 3 architecture and is integrated on TI advanced 45-nm process technology. The architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: • Streaming video • 2-dimension/3-dimension (2D/3D) mobile gaming • Video conferencing • High-resolution still image • Video capture in 2.5G wireless terminals, 3G wireless terminals, rich multimedia-featured handsets, and high-performance personal digital assistants (PDAs) The device supports high-level operating systems (OSs) such as: • Android™ OS • Linux® • Symbian OS™ • Windows® CE This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: • Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor • Imaging video and audio (IVA2.2) subsystem with a TMS320C64x™ digital signal processor (DSP) core • POWERVR® SGX530 subsystem for 2D and 3D graphics acceleration to support display and gaming effects • Camera image signal processor (ISP2P) that supports multiple formats and interfacing options to a wide variety of image sensors • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals The device also offers: • A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption. • Connectivity to various cellular modem chipset • Memory stacking feature using the package-on-package (POP) implementation (see Section 1.4, Package-on-Package Concept)

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OMAP

™

Public Version

OMAP36xx Multimedia Device

Silicon Revision 1.x

Texas Instruments OMAP™ Family of Products

Version U

Technical Reference Manual

Literature Number: SWPU177U

December 2009–Revised June 2011

Public Version

Contents

Preface .................................................................................................................................... 175

1 Introduction .................................................................................................................... 189

1.1 Overview .................................................................................................................. 190

1.2 Environment .............................................................................................................. 191

1.3 Description ................................................................................................................ 193

1.3.1 MPU Subsystem ................................................................................................ 193

1.3.2 IVA2.2 Subsystem .............................................................................................. 194

1.3.3 On-Chip Memory ................................................................................................ 195

1.3.4 External Memory Interfaces ................................................................................... 195

1.3.5 DMA Controllers ................................................................................................. 195

1.3.6 Multimedia ....................................................................................................... 196

1.3.7 Comprehensive Power Management ......................................................................... 197

1.3.8 Peripherals ....................................................................................................... 197

1.4 POP Concept ............................................................................................................. 199

1.5 OMAP36xx Family ....................................................................................................... 200

1.6 Device Identification ..................................................................................................... 202

2 Memory Mapping ............................................................................................................. 205

2.1 Introduction ............................................................................................................... 206

2.2 Global Memory Space Mapping ....................................................................................... 208

2.3 L3 and L4 Memory Space Mapping ................................................................................... 211

2.3.1 L3 Memory Space Mapping ................................................................................... 211

2.3.2 L4 Memory Space Mapping ................................................................................... 212

2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 212

2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 215

2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 216

2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 217

2.3.3 Register Access Restrictions .................................................................................. 218

2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 220

2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 220

2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 220

2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 221

2.4.2 DSP Access to L2 Memories .................................................................................. 222

2.4.2.1 DSP Access to L2 ROM ................................................................................. 222

2.4.2.2 DSP Access to L2 RAM ................................................................................. 222

2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 222

2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 223

2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 223

2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... 225

3 Power, Reset, and Clock Management ................................................................................ 227

3.1 Introduction to Power Managements .................................................................................. 228

3.1.1 Goal of Power Management ................................................................................... 228

3.1.2 Power-Management Techniques ............................................................................. 228

3.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 228

SWPU177U–December 2009–Revised June 2011 Contents

Public Version

www.ti.com

3.1.2.2 SmartReflex Adaptive Voltage Scaling (AVS) ........................................................ 229

3.1.2.3 Dynamic Power Switching ............................................................................... 230

3.1.2.4 Standby Leakage Management ......................................................................... 230

3.1.2.5 DPS Versus SLM ......................................................................................... 231

3.1.2.6 Adaptive Body Bias (ABB) ............................................................................... 231

3.1.2.7 Combining Power-Management Techniques ......................................................... 231

3.1.3 Architectural Blocks for Power Management ................................................................ 232

3.1.3.1 Clock Domain ............................................................................................. 232

3.1.3.2 Power Domain ............................................................................................ 233

3.1.3.3 Voltage Domain ........................................................................................... 234

3.1.4 Device Power-Management Architecture .................................................................... 235

3.1.4.1 Module Interface and Functional Clocks ............................................................... 236

3.1.4.2 Autoidle Clock Control ................................................................................... 237

3.1.5 SmartReflex Voltage-Control Overview ...................................................................... 238

3.1.5.1 Manual SmartReflex Voltage Control .................................................................. 239

3.1.5.2 Automatic SmartReflex Voltage Control ............................................................... 240

3.2 PRCM Overview ......................................................................................................... 241

3.2.1 Introduction ...................................................................................................... 241

3.2.2 PRCM Features ................................................................................................. 243

3.3 PRCM Environment ...................................................................................................... 244

3.3.1 External Clock Signals ......................................................................................... 245

3.3.2 External Reset Signals ......................................................................................... 246

3.3.3 External Power Signals ........................................................................................ 247

3.4 PRCM Integration ........................................................................................................ 248

3.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 251

3.4.1.1 Power Domain ............................................................................................ 251

3.4.1.2 Resets ...................................................................................................... 251

3.4.1.3 Interrupt Requests ........................................................................................ 252

3.5 PRCM Functional Description .......................................................................................... 253

3.5.1 PRCM Reset Manager Functional Description .............................................................. 253

3.5.1.1 Overview ................................................................................................... 253

3.5.1.2 General Characteristics of Reset Signals ............................................................. 253

3.5.1.2.1 Scope .................................................................................................. 254

3.5.1.2.2 Occurrence ............................................................................................ 254

3.5.1.2.3 Source Type .......................................................................................... 254

3.5.1.3 Reset Sources ............................................................................................ 254

3.5.1.3.1 Global Reset Sources ............................................................................... 255

3.5.1.3.2 Local Reset Sources ................................................................................. 256

3.5.1.4 Reset Distribution ......................................................................................... 257

3.5.1.5 Power Domain Reset Descriptions ..................................................................... 258

3.5.1.5.1 MPU Power Domain ................................................................................. 258

3.5.1.5.2 NEON Power Domain ............................................................................... 258

3.5.1.5.3 IVA2 Power Domain ................................................................................. 258

3.5.1.5.4 CORE Power Domain ............................................................................... 258

3.5.1.5.5 DSS Power Domain .................................................................................. 259

3.5.1.5.6 CAM Power Domain ................................................................................. 259

3.5.1.5.7 USBHOST Power Domain .......................................................................... 259

3.5.1.5.8 SGX Power Domain ................................................................................. 259

3.5.1.5.9 WKUP Power Domain ............................................................................... 259

3.5.1.5.10 PER Power Domain ................................................................................. 260

3.5.1.5.11 SmartReflex Power Domain ........................................................................ 260

3.5.1.5.12 DPLL Power Domains ............................................................................... 260

3.5.1.5.13 EFUSE Power Domain .............................................................................. 260

Contents SWPU177U–December 2009–Revised June 2011

Public Version

www.ti.com

3.5.1.5.14 BANDGAP Logic ..................................................................................... 261

3.5.1.5.15 External Warm Reset Assertion .................................................................... 261

3.5.1.6 Reset Logging ............................................................................................. 261

3.5.1.6.1 PRCM Reset Logging Mechanism ................................................................. 261

3.5.1.6.2 SCM Reset Logging ................................................................................. 262

3.5.1.7 Reset Management Overview ........................................................................... 262

3.5.1.8 Reset Summary ........................................................................................... 267

3.5.1.9 Reset Sequences ......................................................................................... 270

3.5.1.9.1 Power-Up Sequence ................................................................................. 270

3.5.1.9.2 Global Warm Reset Sequence ..................................................................... 272

3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence .......................................................... 274

3.5.1.9.4 IVA2 Software Reset Sequence .................................................................... 276

3.5.1.9.5 IVA2 Global Warm Reset Sequence .............................................................. 278

3.5.1.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence .......................................... 280

3.5.2 PRCM Power Manager Functional Description ............................................................. 283

3.5.2.1 Overview ................................................................................................... 283

3.5.2.1.1 Introduction ............................................................................................ 283

3.5.2.1.2 Device Partitioning ................................................................................... 284

3.5.2.1.3 Memory and Logic Power Management .......................................................... 286

3.5.2.1.4 Retention Till Access (RTA) Memory Feature .................................................... 286

3.5.2.1.5 Power Domain States ............................................................................... 287

3.5.2.1.6 Power State Transitions ............................................................................. 287

3.5.2.1.7 Device Power Modes ................................................................................ 288

3.5.2.1.8 Isolation Between Power Domains ................................................................ 288

3.5.2.2 Power Domain Implementation ......................................................................... 288

3.5.2.2.1 Device Power Domains .............................................................................. 288

3.5.2.2.2 Power Domain Memory Status ..................................................................... 290

3.5.2.2.3 Power Domain State Transition Rules ............................................................ 290

3.5.2.2.4 Power Domain Dependencies ...................................................................... 290

3.5.2.2.5 Power Domain Controls ............................................................................. 291

3.5.3 PRCM Clock Manager Functional Description .............................................................. 293

3.5.3.1 Overview ................................................................................................... 293

3.5.3.1.1 Interface and Functional Clocks .................................................................... 294

3.5.3.2 External Clock I/Os ....................................................................................... 295

3.5.3.2.1 External Clock Inputs ................................................................................ 295

3.5.3.2.2 External Clock Outputs .............................................................................. 296

3.5.3.2.3 Summary .............................................................................................. 296

3.5.3.3 Internal Clock Generation ............................................................................... 296

3.5.3.3.1 PRM .................................................................................................... 298

3.5.3.3.2 CM ..................................................................................................... 300

3.5.3.3.3 DPLLs .................................................................................................. 302

3.5.3.3.4 DPLL Clock Summary ............................................................................... 310

3.5.3.3.5 Summary .............................................................................................. 310

3.5.3.4 Clock Distribution ......................................................................................... 311

3.5.3.4.1 Power Domain Clock Distribution .................................................................. 311

3.5.3.4.2 Clock Distribution Summary ........................................................................ 325

3.5.3.5 External Clock Controls .................................................................................. 327

3.5.3.5.1 Clock Request (sys_clkreq) Control ............................................................... 327

3.5.3.5.2 System Clock Oscillator Control .................................................................... 328

3.5.3.5.3 External Output Clock1 (sys_clkout1) Control .................................................... 331

3.5.3.5.4 External Output Clock2 (sys_clkout2) Control .................................................... 331

3.5.3.6 DPLL Control .............................................................................................. 331

3.5.3.6.1 DPLL Multiplier and Divider Factors ............................................................... 331

SWPU177U–December 2009–Revised June 2011 Contents

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2012-08-20

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