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© January 2010 Altera Corporation AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs
AN-477-2.0© January 2010
AN 477: Designing RGMII Interfaces
with FPGAs and HardCopy ASICs
This application note describes how to design a reduced gigabit media independent interface
(RGMII) with Stratix
®
, Arria
®
, and Cyclone
®
FPGAs and HardCopy
®
ASICs.
RGMII is an alternative to the IEEE 802.3z GMII with reduced pin count. Pin count reduction
is achieved by clocking data on both the rising and falling edges of the clock and by
multiplexing the control signals.
1 You must be familiar with RGMII, Synopsys design constraints (SDC), and the
TimeQuest Timing Analyzer before you read this application note.
System-Level Diagram
Figure 1 shows a block diagram of RGMII implementation. An RGMII interface module is
implemented inside an FPGA or HardCopy ASIC and is connected to an external RGMII
PHY. All signals are synchronous with a 125-MHz clock signal.
RGMII data is sampled on both edges of the clock. Ta bl e 1 lists the signal descriptions.
Typically, the clock and data from the RGMII PHY are generated simultaneously, that is,
edge-aligned; thus the clocks must be routed with an added trace delay on the PCB.
Figure 1. Signal Diagram of RGMII
RGMII Module
(FPGA/HardCopy)
External
PHY
TX_CLK
TX_CTL
TXD [3:0]
R
X_
C
L
K
RX_CLK
RX_CTL
RXD [3:0]
Tab le 1 . Signal Description of RGMII (Part 1 of 2)
Signal I/O Type Description
TX_CLK Output Transmit clock from an FPGA and HardCopy ASIC.
TXD Output Bits 3:0 on the positive edge of TX_CLK and bits 7:4 on the negative edge
of TX_CLK.
TX_CTL Output TXEN on the positive edge of TX_CLK and a logical derivative of TXEN
and TXERR on the negative edge of TX_CLK.
RX_CLK Input Receive reference clock from the external PHY.
Page 2 System Timing
AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs © January 2010 Altera Corporation
System Timing
Figure 2 shows the edge-aligned data and clock.
Edge-aligned data requirements complicate the PCB design, such that later revisions
of the RGMII external PHY offer an option to operate with or without internal delay.
This application note reviews the implementations of transmit and receive interfaces
with the RGMII PHY.
RXD Input Bits 3:0 on the positive edge of RX_CLK and bits 7:4 on the negative edge
of RX_CLK.
RX_CTL Input RXDV on the positive edge of RX_CLK and a derivative of RXDV and
RXERR on the negative edge of RXC.
Tab le 1 . Signal Description of RGMII (Part 2 of 2)
Signal I/O Type Description
Figure 2. Timing Diagram for RGMII
TXD[3:0]
TX_CTL
Board delay
Board delay
TX_CLK (at PHY)
RX_CLK (at PHY)
RXD[3:0]
RX_CTL
TX_CLK (at FPGA/HardCopy)
RX_CLK (at FPGA/HardCopy)
Implementation of an FPGA and HardCopy ASIC Transmit Interface Page 3
© January 2010 Altera Corporation AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs
Implementation of an FPGA and HardCopy ASIC Transmit Interface
Implementing the transmit interface is a straight-forward process. Figure 3 shows a
block diagram of the transmit interface.
You can place the interface on any double data input/output (DDIO) I/O register,
through the Altera
®
ALTDDIO_OUT megafunction, as shown in Figure 4.
Figure 3. Block Diagram of Transmit Interface
TXD, TX_CTL
TX_CLK
clk_in
PHYMAC (Altera)
Figure 4. DDIO Megafunction for Transmit Interface
Page 4 Implementation of an FPGA and HardCopy ASIC Transmit Interface
AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs © January 2010 Altera Corporation
For data and clock transmission, most PHY devices that support RGMII offer an
option to add delay to the transmit or receive clock. You can enable or disable this
option based on your design requirements. When you enable the option to delay the
TX_CLK inside the PHY device, the FPGA and HardCopy ASIC must generate a clock
that is edge-aligned with the data and waveforms, as shown in Figure 5.
In this case, the PHY device shifts the clock as necessary to capture the data. When
you disable this option, the FPGA and HardCopy ASIC must generate a clock that is
shifted with respect to the data (typically center-aligned with the data) with board
delay consideration and waveforms, as shown in Figure 6. This shifted clock is used
by the PHY device to capture the data.
You can use various methods to align the sourced clock with the data. You can drive
clocks by the same clock that registers the data or that was created by a toggling clock
output register, such as in the ALTDDIO_OUT megafunction. When the output clocks
are generated independently from the data output register clocks (for example, two
phase-locked loop [PLL] taps), you can change the clock and data timing relationship
by adjusting the relationship between their clocks (for example, adjusting PLL phase).
You can achieve this with Altera’s PLL megafunction.
Figure 5. FPGA-Generated TX_CLK When TX_CLK Delay is Enabled in the PHY
TXD[3:0] @ FPGA/HardCopy
TX_CLK @ FPGA/HardCopy
Figure 6. FPGA-Generated TX_CLK When TX_CLK Delay is Disabled in the PHY
TXD[3:0] @ FPGA/HardCopy
TX_CLK @ FPGA/HardCopy
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