© January 2010 Altera Corporation AN 477: Designing RGMII Interfaces with FPGAs and HardCopy ASICs
AN-477-2.0© January 2010
AN 477: Designing RGMII Interfaces
with FPGAs and HardCopy ASICs
This application note describes how to design a reduced gigabit media independent interface
(RGMII) with Stratix
®
, Arria
®
, and Cyclone
®
FPGAs and HardCopy
®
ASICs.
RGMII is an alternative to the IEEE 802.3z GMII with reduced pin count. Pin count reduction
is achieved by clocking data on both the rising and falling edges of the clock and by
multiplexing the control signals.
1 You must be familiar with RGMII, Synopsys design constraints (SDC), and the
TimeQuest Timing Analyzer before you read this application note.
System-Level Diagram
Figure 1 shows a block diagram of RGMII implementation. An RGMII interface module is
implemented inside an FPGA or HardCopy ASIC and is connected to an external RGMII
PHY. All signals are synchronous with a 125-MHz clock signal.
RGMII data is sampled on both edges of the clock. Ta bl e 1 lists the signal descriptions.
Typically, the clock and data from the RGMII PHY are generated simultaneously, that is,
edge-aligned; thus the clocks must be routed with an added trace delay on the PCB.
Figure 1. Signal Diagram of RGMII
RGMII Module
(FPGA/HardCopy)
External
PHY
TX_CLK
TX_CTL
TXD [3:0]
R
X_
C
L
K
RX_CLK
RX_CTL
RXD [3:0]
Tab le 1 . Signal Description of RGMII (Part 1 of 2)
Signal I/O Type Description
TX_CLK Output Transmit clock from an FPGA and HardCopy ASIC.
TXD Output Bits 3:0 on the positive edge of TX_CLK and bits 7:4 on the negative edge
of TX_CLK.
TX_CTL Output TXEN on the positive edge of TX_CLK and a logical derivative of TXEN
and TXERR on the negative edge of TX_CLK.
RX_CLK Input Receive reference clock from the external PHY.
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