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MIPI C-PHY is developed by the MIPI PHY Working Group. Operation and available data rates for a link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs. Bi-directional and half-duplex operation are optional.
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Specification for
C-PHY
Vers
ion 1.0 – 05 August 2014
MIPI Board Adopted 07 October 2014
* NOTE TO IMPLEMENTERS *
This document is a Specification. MIPI member companies’ rights and obligations apply to this Specification as defined
in the MIPI Membership Agreement and MIPI Bylaws.
Copyright © 2013-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential
SM

This
page intentionally left blank.
Copyright © 2013-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential

Specification for
C-PHY
Version
1.0
05 August 201
4
MIPI Board Adopted 07 October
2014
Further technical changes to this document are expected as work continues in the
C-PHY Subgroup of
the PHY
Working Group.
Copyright © 2013-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential
SM

Specification for C-PHY Version 1.0
05-Aug-2014
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled
by any of the authors or developers of this material or MIPI
®
. The material contained herein is provided on
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any)
implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or
completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior
written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
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cannot be used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS
OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT,
TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER
AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR
NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may involve
or require the use of intellectual property rights (“IPR”) including (but not limited to) patents, patent
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make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or
claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
ii Copyright © 2013-2014 MIPI Alliance, Inc.
All rights reserved.
Confidential

Version 1.0 Specification for C-PHY
05-Aug-2014
Contents
1 Introduction .................................................................................................................1
1.1 Scope ............................................................................................................................... 1
1.2 Purpose ............................................................................................................................ 2
2 Terminology .................................................................................................................3
2.1 Use of Special Terms ....................................................................................................... 3
2.2 Definitions ....................................................................................................................... 3
2.3 Abbreviations ................................................................................................................... 4
2.4 Acronyms ......................................................................................................................... 4
3 References ....................................................................................................................6
4 C-PHY Overview .........................................................................................................7
4.1 Summary of PHY Functionality ...................................................................................... 7
4.1.1 Summary of Lane Signaling States .............................................................................. 7
4.1.2 Representation of Symbols in High-Speed Mode ........................................................ 9
4.1.3 Representation of High-Speed Signaling States ......................................................... 10
4.2 Mandatory Functionality ............................................................................................... 10
5 Architecture ............................................................................................................... 11
5.1 Lane Modules ................................................................................................................ 11
5.2 Master and Slave ............................................................................................................ 12
5.3 High Frequency Clock Generation ................................................................................ 12
5.4 Lanes and the PHY-Protocol Interface ........................................................................... 12
5.5 Selectable Lane Options ................................................................................................ 13
5.6 Lane Module Types ....................................................................................................... 15
5.6.1 Unidirectional Lane .................................................................................................... 16
5.6.2 Bi-directional Lanes ................................................................................................... 16
5.7 Configurations ............................................................................................................... 16
5.7.1 Unidirectional Configurations .................................................................................... 17
5.7.2 Bi-Dire
ctional Half-Duplex Configurations ............................................................... 19
6 Global Operation .......................................................................................................21
6.1 Transmission Data Structure .......................................................................................... 21
6.1.1 Data Units ................................................................................................................... 21
6.1.2 Bit order, Serialization, and De-Serialization ............................................................. 21
6.1.3 Encoding, Decoding, Mapping and De-Mapping ....................................................... 21
6.1.4 Data Buffering ............................................................................................................ 32
6.2 Lane States and Line Levels .......................................................................................... 33
6.3 Operating Modes: Control, High-Speed, and Escape .................................................... 34
6.4 High-Speed Data Transmission ..................................................................................... 34
6.4.1 Burst Payload Data ..................................................................................................... 34
6.4.2 Start-of-Transmission ................................................................................................. 34
6.4.3 End-of-Transmission .................................................................................................. 35
6.4.4 HS Data Transmission Burst....................................................................................... 35
6.5 Bi-directional Lane Turnaround..................................................................................... 41
6.6 Escape Mode .................................................................................................................. 43
6.6.1 Remote Triggers ......................................................................................................... 44
6.6.2 Low-Power Data Transmission .................................................................................. 45
Copyright © 2013-2014 MIPI Alliance, Inc. iii
All rights reserved.
Confidential
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