旋转编码器verilog程序

module rotencoder(A,B,clk,reset,output8,lock,cs); input clk,A,B,reset,lock,cs; output[7:0] output8; reg[15:0] count; reg[15:0] out_lock; reg[7:0] output_8; reg A1,B1,A2,B2,cs1,cs2; always@(posedge clk)