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RapidIO转PCIe的桥接芯片资料
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IDT公司的SRIO转PCIe的桥接芯片,通过该芯片可以轻松实现SRIO系统与PCIe系统的无缝连接,实现两个生态系统的融合。
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®
Tsi721
™
User Manual
Formal
October 2, 2012
Titl
IDT Confidential
wy2011@bnc.com.cn
March 31, 2013
GENERAL DISCLAIMER
Integrated Device Technology, Inc. (“IDT”) reserves the right to make changes to its products or specifications at any time, without notice,
in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the
circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or
otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product
performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as
“reserved” or “undefined” are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising
from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not
warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury,
or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for
developing applications. Any use of such code examples shall be at the user's sole risk.
Copyright ©2012 Integrated Device Technology, Inc.
The IDT logo is registered to Integrated Device Technology, Inc.
“Accelerated Thinking” is a service mark of Integrated Device Technology, Inc.
IDT Confidential
wy2011@bnc.com.cn
March 31, 2013
Tsi721 User Manual 3 October 2, 2012
Formal This document is confidential and is subject to an NDA.
Integrated Device Technology
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Overview.................................................................................................................................................................................................. 26
Document Conventions............................................................................................................................................................................ 26
Revision History....................................................................................................................................................................................... 27
Overview
1. Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.1 Overview.................................................................................................................................................................................................. 31
1.2 Features................................................................................................................................................................................................... 31
1.2.1 PCIe Features .......................................................................................................................................................................... 31
1.2.2 S-RIO Features ........................................................................................................................................................................ 32
1.2.3 Bridging Features.....................................................................................................................................................................32
1.2.4 Messaging Features................................................................................................................................................................. 33
1.2.5 Block DMA Engine Features .................................................................................................................................................... 33
1.2.6 Miscellaneous Features............................................................................................................................................................ 34
1.3 Block Diagram.......................................................................................................................................................................................... 35
1.3.1 PCIe Interface........................................................................................................................................................................... 35
1.3.2 S-RIO Interface......................................................................................................................................................................... 35
1.3.3 Messaging Engine.................................................................................................................................................................... 35
1.3.4 Mapping Engine........................................................................................................................................................................ 35
1.3.5 Block DMA Engine.................................................................................................................................................................... 35
1.4 Typical Applications ................................................................................................................................................................................. 36
1.4.1 Defence/Aerospace Application ............................................................................................................................................... 36
1.4.2 Video and Imaging Application................................................................................................................................................. 38
1.4.3 Wireless Application ................................................................................................................................................................. 38
2. Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.1 Overview.................................................................................................................................................................................................. 40
2.1.1 PCIe to S-RIO Bridging Data Path ........................................................................................................................................... 42
2.1.2 S-RIO to PCIe Bridging Data Path ........................................................................................................................................... 44
2.1.3 Messaging Engine Data Path................................................................................................................................................... 47
2.1.4 Block DMA Engine Data Path................................................................................................................................................... 48
2.2 Ordering Rules......................................................................................................................................................................................... 51
2.2.1 Device Ordering Rules ............................................................................................................................................................. 51
2.2.2 Application Enforced Inter-Data Path Synchronization............................................................................................................. 56
2.3 Loopbacks ...............................................................................................................................................................................................57
2.3.1 PCIe Master Loopback............................................................................................................................................................. 57
2.3.2 PCIe 8-bit PRBS Master Loopback.......................................................................................................................................... 59
2.3.3 PCIe Slave Loopback............................................................................................................................................................... 60
2.3.4 PCIe 10-bit PCS Slave Loopback.............................................................................................................................................61
2.3.5 PCIe PMA Loopback ................................................................................................................................................................ 62
C
o
IDT Confidential
wy2011@bnc.com.cn
March 31, 2013
Table of Contents
Tsi721 User Manual 4 October 2, 2012
Formal This document is confidential and is subject to an NDA.
Integrated Device Technology
2.3.6 PCIe Application Layer Loopback ............................................................................................................................................ 62
2.3.7 S-RIO Line Loopback............................................................................................................................................................... 63
2.3.8 S-RIO Digital Equipment Loopbacks........................................................................................................................................ 64
2.3.9 S-RIO PMA Loopback.............................................................................................................................................................. 64
2.4 Performance ............................................................................................................................................................................................ 65
2.4.1 Throughput Measurements ...................................................................................................................................................... 65
2.4.2 Latency Measurements ............................................................................................................................................................ 66
2.5 Endian Conversion .................................................................................................................................................................................. 66
2.5.1 Address Invariant Endian Conversion for Payload................................................................................................................... 66
2.5.2 Register Endian Conversion..................................................................................................................................................... 66
2.6 Data Protection........................................................................................................................................................................................ 67
3. Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
3.1 Overview.................................................................................................................................................................................................. 68
3.2 Ballmap.................................................................................................................................................................................................... 69
3.3 Pinlist ....................................................................................................................................................................................................... 70
3.4 PCIe Signals............................................................................................................................................................................................ 70
3.5 S-RIO Signals.......................................................................................................................................................................................... 71
3.6 General Signals ....................................................................................................................................................................................... 71
3.7 I2C Signals .............................................................................................................................................................................................. 72
3.8 JTAG and Test Interface Signals.............................................................................................................................................................. 72
3.9 GPIO Signals........................................................................................................................................................................................... 73
3.10 Power-up Signals..................................................................................................................................................................................... 74
3.11 Power Supply Signals..............................................................................................................................................................................77
PCIe Interface
4. PCIe Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
4.1 Features................................................................................................................................................................................................... 79
4.1.1 Unsupported Optional PCIe Features ...................................................................................................................................... 80
4.2 Physical Layer ......................................................................................................................................................................................... 80
4.3 Data Link Layer........................................................................................................................................................................................ 81
4.4 Base Address Registers .......................................................................................................................................................................... 81
4.5 TLP Receive Processing.......................................................................................................................................................................... 81
4.5.1 Memory Read Request (MRd).................................................................................................................................................. 82
4.5.2 Memory Write Request (MWr).................................................................................................................................................. 82
4.5.3 Configuration Read Type 0 (CfgRd0) ....................................................................................................................................... 82
4.5.4 Configuration Write Type 0 (CfgWr0) ....................................................................................................................................... 82
4.5.5 Configuration Read and Write Type 1 (CfgRd1 and CfgWr1)................................................................................................... 82
4.5.6 Assert_INTx and Deassert_INTx.............................................................................................................................................. 82
4.5.7 PM_Active_State_Nak.............................................................................................................................................................. 82
4.5.8 PM_PME .................................................................................................................................................................................. 82
4.5.9 PME_Turn_Off.......................................................................................................................................................................... 83
4.5.10 PME_TO_Ack........................................................................................................................................................................... 83
4.5.11 Error Messages (ERR_COR, ERR_NONFATAL, and ERR_FATAL)........................................................................................ 83
4.5.12 Unlock....................................................................................................................................................................................... 83
4.5.13 Set_Slot_Power_Limit.............................................................................................................................................................. 83
4.5.14 Vendor-Defined Messages....................................................................................................................................................... 83
IDT Confidential
wy2011@bnc.com.cn
March 31, 2013
Table of Contents
Tsi721 User Manual 5 October 2, 2012
Formal This document is confidential and is subject to an NDA.
Integrated Device Technology
4.6 Transmit TLP Processing......................................................................................................................................................................... 83
4.7 Buffers...................................................................................................................................................................................................... 84
4.7.1 Ingress Frame Buffer................................................................................................................................................................ 84
4.7.2 Egress Frame Buffer ................................................................................................................................................................ 84
4.8 Device Power Management..................................................................................................................................................................... 85
4.8.1 PME Messages ........................................................................................................................................................................ 86
4.8.2 PCIe Power Management Fence Protocol............................................................................................................................... 86
5. Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
5.1 Overview.................................................................................................................................................................................................. 87
5.2 Interrupt Sources ..................................................................................................................................................................................... 89
5.3 MSI-X....................................................................................................................................................................................................... 89
5.3.1 MSI-X Vector Assignment ........................................................................................................................................................ 90
5.4 MSI .......................................................................................................................................................................................................... 92
5.4.1 MSI Vector 0 Interrupt Hierarchy .............................................................................................................................................. 92
5.5 INTx ......................................................................................................................................................................................................... 97
5.5.1 INTx Interrupt Hierarchy...........................................................................................................................................................97
5.6 Interrupt Moderation .............................................................................................................................................................................. 101
5.7 PCIe Advisory Error Reporting............................................................................................................................................................... 101
5.7.1 Physical Layer Errors ............................................................................................................................................................. 101
5.7.2 Data Link Layer Errors............................................................................................................................................................ 101
5.7.3 Transaction Layer Errors........................................................................................................................................................ 102
5.7.4 AER Emulation.......................................................................................................................................................................106
5.8 SMBus Alert Response Hierarchy ......................................................................................................................................................... 107
RapidIO Interface
6. S-RIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
6.1 Features..................................................................................................................................................................................................112
6.1.1 Unsupported Optional S-RIO Features ...................................................................................................................................113
6.2 Physical Layer ........................................................................................................................................................................................113
6.2.1 Changing S-RIO Port Link Rate ..............................................................................................................................................113
6.2.2 Bit Error Rate Testing (BERT) .................................................................................................................................................113
6.3 Transport Layer.......................................................................................................................................................................................115
6.3.1 destID Filtering ........................................................................................................................................................................115
6.3.2 ftype Filtering...........................................................................................................................................................................115
6.4 S-RIO Egress Packet Buffer (PBMe)......................................................................................................................................................115
6.4.1 CRQ Reordering......................................................................................................................................................................115
6.5 S-RIO Ingress Packet Buffer (PBMi).......................................................................................................................................................116
6.5.1 ftype/ttype Filtering..................................................................................................................................................................116
6.6 Local Logical Layer Management...........................................................................................................................................................116
6.6.1 Maintenance Read/Write Request...........................................................................................................................................117
6.6.2 Maintenance Read/Write Response........................................................................................................................................118
6.6.3 Maintenance Port-Write Request ............................................................................................................................................119
7. S-RIO Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
7.1 Overview................................................................................................................................................................................................ 121
7.2 Event Notification................................................................................................................................................................................... 121
7.2.1 Event Detection and Notification Summary............................................................................................................................ 122
7.2.2 Hierarchy of Event Detection.................................................................................................................................................. 131
IDT Confidential
wy2011@bnc.com.cn
March 31, 2013
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