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MIPI-DSI-specification-v1-1
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本pdf文档针对sony IMX系列sensor中涉及到的知识点进行细分。是sensor设计不可或缺的参考技术文件。与大家分享,共同学习。
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6-Apr-2012
Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
MIPI
®
Alliance Specification for
Display Serial Interface (DSI)
Version 1.1 – 22 November 2011
* NOTE TO IMPLEMENTERS *
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to
this MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
Version 1.1 22-Nov-2011 MIPI Alliance Specification for DSI
Copyright © 2005-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
MIPI
®
Alliance Specification for
Display Serial Interface (DSI)
Version 1.1 – 22 November 2011
MIPI Board Approved 14-Mar-2012
Further technical changes to this document are expected as work continues in the Display Working Group
Version 1.1 22-Nov-2011 MIPI Alliance Specification for DSI
Copyright © 2005-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
ii
NOTICE OF DISCLAIMER 1
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled 2
by any of the authors or developers of this material or MIPI
®
. The material contained herein is provided on 3
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 4
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 5
other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if 6
any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of 7
accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of 8
negligence. 9
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, 10
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express 11
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related 12
trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and 13
cannot be used without its express prior written permission. 14
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET 15
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 16
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY 17
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 18
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE 19
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 20
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER 21
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR 22
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, 23
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH 24
DAMAGES. 25
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is 26
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the 27
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; 28
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance 29
with the contents of this Document. The use or implementation of the contents of this Document may 30
involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, 31
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI 32
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any 33
IPR or claims of IPR as respects the contents of this Document or otherwise. 34
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 35
MIPI Alliance, Inc. 36
c/o IEEE-ISTO 37
445 Hoes Lane 38
Piscataway, NJ 08854 39
Attn: Board Secretary 40
Version 1.1 22-Nov-2011 MIPI Alliance Specification for DSI
Copyright © 2005-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iii
Contents 41
Version 1.1 – 22 November 2011 ............................................................................................................... i
42
1
Overview ........................................................................................................................................ 11 43
1.1
Scope ...................................................................................................................................... 11 44
1.2
Purpose ................................................................................................................................... 11 45
2
Terminology (informative) .............................................................................................................. 12 46
2.1
Definitions .............................................................................................................................. 12 47
2.2
Abbreviations .......................................................................................................................... 13 48
2.3
Acronyms ............................................................................................................................... 13 49
3
References (informative) ................................................................................................................. 16 50
3.1
Display Bus Interface Standard for Parallel Signaling (DBI-2) ................................................. 16 51
3.2
Display Pixel Interface Standard for Parallel Signaling (DPI-2) ................................................ 17
52
3.3
MIPI Alliance Specification for Display Command Set (DCS) ................................................. 17 53
3.4
MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) ................................................. 17 54
3.5
MIPI Alliance Specification for D-PHY (D-PHY).................................................................... 17
55
3.6
MIPI Alliance Specification for Stereoscopic Display Formats (SDF) ...................................... 18 56
4
DSI Introduction ............................................................................................................................. 19 57
4.1
DSI Layer Definitions ............................................................................................................. 20 58
4.2
Command and Video Modes.................................................................................................... 21 59
4.2.1
Command Mode .............................................................................................................. 21 60
4.2.2
Video Mode Operation ..................................................................................................... 21 61
4.2.3
Virtual Channel Capability ............................................................................................... 22 62
5
DSI Physical Layer ......................................................................................................................... 23 63
5.1
Data Flow Control ................................................................................................................... 23
64
5.2
Bidirectionality and Low Power Signaling Policy .................................................................... 23 65
5.3
Command Mode Interfaces ...................................................................................................... 24 66
5.4
Video Mode Interfaces ............................................................................................................ 24 67
5.5
Bidirectional Control Mechanism ............................................................................................ 24 68
5.6
Clock Management ................................................................................................................. 25 69
5.6.1
Clock Requirements ......................................................................................................... 25 70
5.6.2
Clock Power and Timing.................................................................................................. 26 71
5.7
System Power-Up and Initialization ......................................................................................... 26 72
6
Multi-Lane Distribution and Merging .............................................................................................. 28 73
6.1
Multi-Lane Interoperability and Lane-number Mismatch.......................................................... 29 74
6.1.1
Clock Considerations with Multi-Lane ............................................................................. 30 75
6.1.2
Bidirectionality and Multi-Lane Capability ....................................................................... 30 76
Version 1.1 22-Nov-2011 MIPI Alliance Specification for DSI
Copyright © 2005-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iv
6.1.3 SoT and EoT in Multi-Lane Configurations ...................................................................... 30 77
7
Low-Level Protocol Errors and Contention ...................................................................................... 33 78
7.1
Low-Level Protocol Errors ...................................................................................................... 33 79
7.1.1
SoT Error ........................................................................................................................ 33 80
7.1.2
SoT Sync Error ................................................................................................................ 34 81
7.1.3
EoT Sync Error ................................................................................................................ 34 82
7.1.4
Escape Mode Entry Command Error ................................................................................ 35 83
7.1.5
LP Transmission Sync Error ............................................................................................ 35 84
7.1.6
False Control Error .......................................................................................................... 35 85
7.2
Contention Detection and Recovery ......................................................................................... 36 86
7.2.1
Contention Detection in LP Mode .................................................................................... 36 87
7.2.2
Contention Recovery Using Timers .................................................................................. 36 88
7.3
Additional Timers ................................................................................................................... 39 89
7.3.1
Turnaround Acknowledge Timeout (TA_TO) ................................................................... 39 90
7.3.2
Peripheral Reset Timeout (PR_TO) .................................................................................. 39 91
7.3.3
Peripheral Response Timeout (PRESP_TO) ..................................................................... 40 92
7.4
Acknowledge and Error Reporting Mechanism ........................................................................ 40 93
8
DSI Protocol ................................................................................................................................... 42
94
8.1
Multiple Packets per Transmission .......................................................................................... 42
95
8.2
Packet Composition................................................................................................................. 43 96
8.3
Endian Policy .......................................................................................................................... 44 97
8.4
General Packet Structure ......................................................................................................... 44
98
8.4.1
Long Packet Format ......................................................................................................... 44 99
8.4.2
Short Packet Format ......................................................................................................... 46 100
8.5
Common Packet Elements ....................................................................................................... 46
101
8.5.1
Data Identifier Byte ......................................................................................................... 46 102
8.5.2
Error Correction Code ...................................................................................................... 47 103
8.6
Interleaved Data Streams ......................................................................................................... 48 104
8.6.1
Interleaved Data Streams and Bidirectionality .................................................................. 48 105
8.7
Processor to Peripheral Direction (Processor-Sourced) Packet Data Types................................ 49 106
8.8
Processor-to-Peripheral Transactions – Detailed Format Description ........................................ 50 107
8.8.1
Sync Event (H Start, H End, V Start, V End), Data Type = XX 0001 (0xX1) .................... 50 108
8.8.2
EoTp, Data Type = 00 1000 (0x08) .................................................................................. 51 109
8.8.3
Color Mode Off Command, Data Type = 00 0010 (0x02) ................................................. 52 110
8.8.4
Color Mode On Command, Data Type = 01 0010 (0x12) .................................................. 52 111
8.8.5
Shutdown Peripheral Command, Data Type = 10 0010 (0x22) .......................................... 52 112
8.8.6
Turn On Peripheral Command, Data Type = 11 0010 (0x32) ............................................ 53 113
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