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首页JESD 204B 协议规范
随着转换器分辨率和速度的提高,对更高效率接口的需求也随之增长。JESD204接口可提供这种高效率,较之CMOS和LVDS接口产品在速度、尺寸和成本上更有优势。采用JESD204的设计具有更高的接口速率,能支持转换器的更高采样速率。此外,引脚数量的减少使得封装尺寸更小且布线数量更少,这些都让电路板更容易设计并且整体系统成本更低。该标准可以方便地调整,从而满足未来需求. 2006年4月,JESD204最初版本发布。该版本描述了转换器和接收器(通常是FPGA或ASIC)之间几个G比特的串行数据链路。
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JEDEC
STANDARD
Serial Interface for Data Converters
JESD204B
(Revision of JESD204A, April 2008)
JULY 2011
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under
Standards and Documents for alternative contact information.
Published by
©JEDEC Solid State Technology Association 2011
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Arlington, VA 22201-2107
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
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This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street
Suite 240 South
Arlington, VA 22201-2107
or refer to www.jedec.org under Standards and Documents
for alternative contact information.
JEDEC Standard No. 204B
Page 1
SERIAL INTERFACE FOR DATA CONVERTERS
(From JEDEC Board Ballot JCB-08-01 and JCB-11-47, formulated under the cognizance of JC-16
Committee on Interface Technology.)
1 Scope
This specification describes a serialized interface between data converters and logic devices. It contains
normative information to enable designers to implement devices that communicate with other devices
covered by this specification. Informative annexes are included to clarify and exemplify the specification.
Due to the range of applications involved, the intention of the document is to completely specify only the
serial data interface and the link protocol. Certain signals common to both the interface and the function
of the device, such as device clocks and control interfaces, have application-dependent requirements.
Devices may also have application-dependent modes, such as a low power / shutdown mode that will
affect the interface. In these instances, the specification merely constrains other device properties as they
relate to the interface, and leaves the specific implementation up to the designer.
Revision A of the standard was expanded to support serial data interfaces consisting of single or multiple
lanes per converter device. In addition, converter functionality (ADC or DAC) can be distributed over
multiple devices:
• All parallel running devices are implemented or specified to run synchronously with each other using
the same data format.
• Normally this means that they are part of the same product family.
Revision B of the standard now supports the following additional functions:
• Mechanism for achieving repeatable, programmable deterministic delay across the JESD204 link.
• Support for serial data rates up to 12.5 Gbps.
• Transition from using frame clock as the main clock source to using device clock as the main clock
source. Device clock frequency requirements offer much more flexibility compared to requiring a
frame clock input.
The logic device (e.g. ASIC or FPGA) is always assumed to be a single device.
Figure
1 compares the scope of the original JESD204 specification and its revisions.
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