Preliminary DFI 4.0 Specification, Version 2
January 30, 2015 16 | Page
LPDDR4 Channel
(and might be different), special handling is required for the various interfaces. The following paragraphs discuss the
implications of having independent responses on these interfaces.
For combined operation with the PHY connected to both command channels, Figure 5 remains unchanged. The command
signals from the MC to the PHY are identical for both channels. The signals from the PHY to the MC might or might not
be identical.
Figure 6 illustrates connecting an LPDDR4 device for combined channels, with a single control interface connecting to
both channels. The MC can represent one or two memory controllers.
FIGURE 6. LPDDR4 Combined Channels
For combined operations, the control interface, read data interface control signals, and write data interface control signals
that the MC drives operate in lock-step. In general, other MC-driven signals also operate in lock-step, unless defined
otherwise. Some signals, such as dfi_freq_ratio, must drive the same value. Other interfaces, discussed later, require
some special considerations in a combined configuration when using the interfaces from both channels, if the channels are
not required to be driven identically. Using both channels for some interfaces and only a single channel for other
interfaces is permitted. Unused interfaces should be tied inactive.
NOTE: A channel can be disabled, but not a single interface within a channel.
The update interface can be driven uniquely by the two channels. The controller update must be driven identically to both
channels. If the PHY on one channel asserts the acknowledge and the other channel does not respond, or if the
acknowledges from the channels are de-asserted at different times, both DFI channels remain idle until the update is
completed on both channels. If the PHY update request is asserted differently on the two channels, when the MC
acknowledges, both channels must remain idle. When the MC acknowledges the PHY update request, the acknowledge
will be asserted to one or both channels, depending on whether one or both requests are asserted. When the acknowledge
is asserted, no additional PHY update requests can be serviced until the update in progress completes.
At the status interface, initialization does not complete until both channels assert dfi_init_complete. For frequency
change, the MC requests a frequency change in lock-step by asserting dfi_init_start to both channels. If one channel
acknowledges and the other channel does not acknowledge, the MC terminates the frequency change on the channel that
acknowledged by de-asserting dfi_init_start without changing the clock frequency. Both channels must wait for the
completion of the frequency change handshake on the acknowledging channel before running additional commands. The
dfi_freq_ratio signal must be identical for both channels.
DFI Command 0
MC
PHY
CMD
PHY
D0
PHY
D1
DFI Data 1
DFI Data 0
DR AM
Ch0
DR AM
Ch1
DFI Command 1
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