VESAeDP_v1_3(EmbeddeddisplayPortStandard)_DisplayPortdual-mode

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VESA Embedded DisplayPort Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.3

eDP

39899 Balentine Drive, Suite 125 Phone: 510 651 5122

Newark, CA 94560 Fax: 510 651 5127

URL: www.vesa.org

VESA Embedded DisplayPort Standard

Version 1.3

13 January 2011

Purpose

This standard defines requirements and options of a standardized display panel interface for embedded display

applications. It is based on the VESA DisplayPort Standard Version 1.2 and includes implementation options

recommended for consideration by the system integrator.

Summary

DisplayPort 1.2 is a scalable and extendable video data interface developed for use in both embedded (internal)

and external (box-to-box) applications. While DisplayPort™ does reference embedded applications; it is primarily

oriented toward external applications with emphasis on interoperability between system vendors and interconnect

cables. This standard defines a feature set of an embedded version of DisplayPort for applications including, but

not limited to, notebook PCs and all-in-one PCs.

VESA Embedded DisplayPort Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.3

Table of Contents

Purpose .................................................................................................................................................. 1!

Summary ................................................................................................................................................ 1!

Preface ................................................................................................................................................... 6!

Acknowledgements ................................................................................................................................ 8!

Revision History .................................................................................................................................... 9!

1! Overview ........................................................................................................................................ 11!

1.1! Background .............................................................................................................................. 11!

1.2! Acronyms ................................................................................................................................. 12!

1.3! Glossary ................................................................................................................................... 13!

1.4! References ................................................................................................................................ 15!

2! eDP System Architecture ............................................................................................................... 16!

2.1! eDP System Application .......................................................................................................... 16!

2.2! eDP Support by Source and Sink Components ....................................................................... 16!

3! Embedded DisplayPort Implementation ........................................................................................ 17!

3.1! Background .............................................................................................................................. 17!

3.2! eDP Feature Requirements and Recommendations ................................................................. 17!

3.3! Number of Main Link Lanes vs. Video Mode Support (Informative) .................................... 19!

3.4! eDP AUX Link Services .......................................................................................................... 21!

3.5! PSR Secondary Data Packet Support ...................................................................................... 37!

3.6! Support for Display Authentication and Content Protection ................................................... 39!

3.7! Panel Input Power (LCDVCC) ................................................................................................ 46!

3.8! Main Stream Attribute Data ..................................................................................................... 46!

3.9! Display Backlight Control Using DPCD Registers ................................................................. 47!

3.10! LCD Panel Self-Test (Informative) ......................................................................................... 52!

4! Panel Self Refresh (PSR) ............................................................................................................... 54!

4.1! Architecture Overview ............................................................................................................. 54!

4.1.1! Source Responsibilities ................................................................................................................. 55!

4.1.2! Sink Responsibilities ..................................................................................................................... 55!

4.2! Configuration ........................................................................................................................... 56!

4.3! PSR Entry/Exit Protocols ........................................................................................................ 57!

4.3.1! PSR States ..................................................................................................................................... 57!

4.3.2! PSR Entry ...................................................................................................................................... 60!

4.3.3! PSR Exit ........................................................................................................................................ 62!

4.3.4! PSR Entry Abort ........................................................................................................................... 65!

4.3.5! Single Frame Updates .................................................................................................................. 66!

VESA Embedded DisplayPort Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.3

Tables

Table 1: Main Contributors to Version 1.3 ....................................................................................................... 8!

Table 1-1: Reference Documents ..................................................................................................................... 15!

Table 3-1: eDP Features and Recommended Configurations ........................................................................... 17!

Table 3-2: Bit Rate Capacity for Possible eDP Main Link Configurations (Informative) ............................... 19!

Table 3-3: Supported Video Mode Examples for Common eDP Configurations (Informative) ..................... 20!

Table 3-4: Assignment of DPCD Register 0000Dh Bit 3 within eDP v1.2 ..................................................... 21!

Table 3-5: Display Control DPCD Registers Listed as Reserved within DisplayPort v1.2 ............................. 23!

Table 3-6: DPCD – Sink PSR Capability Field ................................................................................................ 32!

Table 3-7: DPCD – Sink PSR Configuration Field .......................................................................................... 33!

Table 3-8: DPCD – Sink PSR Status Field ....................................................................................................... 34!

Table 3-9: Video Stream Configuration Packet ................................................................................................ 38!

Table 3-10: Video Stream Configuration Packet Header ................................................................................. 38!

Table 3-11: Video Stream Configuration Packet DB1 ..................................................................................... 39!

Table 3-12: Video Stream Configuration Packet DB2-3 .................................................................................. 39!

Table 3-13: Video Stream Configuration Packet DB4-5 .................................................................................. 39!

Table 3-14: Video Stream Configuration Packet DB6-7 .................................................................................. 39!

Table 3-15: Optional eDP Display Authentication and Content Protection Methods ...................................... 40!

Table 3-16: Expanded Description of Figure 3-6 ............................................................................................. 46!

Table 3-17: Set of MSA Timing Parameters That May Be Ignored ................................................................. 46!

Table 3-18: DPCD Register Bits That Determines Use of Parameters in Table 3-17 ...................................... 47!

Table 3-19: Summary of Backlight Control Modes Using DPCD Registers in Table 3-5 ................................ 50!

Table 3-20: LCD Self-Test Color Square Definition ....................................................................................... 53!

Table 4-1: Sink Action for Single Frame Update .............................................................................................. 66!

Table 5-1: eDP Panel Power Sequence Timing Parameters ............................................................................. 72!

Table 6-1: 20-Pin eDP Pin Assignment for CCFL Backlight (1 or 2 Lane eDP) ............................................. 74!

Table 6-2: 30-Pin eDP Pin Assignment for LED Backlight w/o LED Driver on PCB (1 or 2 Lane eDP) ...... 75!

Table 6-3: 30-Pin eDP Pin Assignment for LED Backlight with LED Driver on PCB (1 or 2 Lane eDP) ..... 76!

Table 6-4: 40-Pin eDP Pin Assignment for LED Backlight with LED Driver on PCB (up to 4 Lane eDP) ... 77!

Table 8-1: Main Contributors to Version 1 ...................................................................................................... 79!

Table 8-2: Main Contributors to Version 1.1a .................................................................................................. 80!

Table 8-3: Main Contributors to Version 1.2 ................................................................................................... 81!

VESA Embedded DisplayPort Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.3

Figures

Figure 2-1: Typical System Implementation of eDP ........................................................................................ 16!

Figure 3-1: Recommended eDP AUX Channel Topology ............................................................................... 18!

Figure 3-2: Example of a Single eDP Panel Supporting Multiple Source Display Authentication Methods .. 41!

Figure 3-3: eDP Panel Factory Production Process Operational Example ....................................................... 42!

Figure 3-4: eDP Panel Embedded in Notebook PC Operational Example ....................................................... 43!

Figure 3-5: eDP Panel Field Service Process Operational Example ................................................................ 44!

Figure 3-6: Method 3a or 3b Identification and Control During Link Training Process ................................. 45!

Figure 3-7: Control of Backlight via Timing Controller .................................................................................. 48!

Figure 3-8: Control of Backlight via eDP Connector Interface ........................................................................ 49!

Figure 3-9: TCON Circuit Blocks the Determine Panel Backlight Frequency ................................................ 51!

Figure 3-10: LCD Panel Self-Test Patterns ...................................................................................................... 53!

Figure 4-1: Panel Self Refresh System-level Diagram ...................................................................................... 54!

Figure 4-3: PSR Configuration .......................................................................................................................... 56!

Figure 4-4: Source PSR States ........................................................................................................................... 58!

Figure 4-5: Sink PSR States .............................................................................................................................. 59!

Figure 4-6: PSR Entry for Source TX Off Case ................................................................................................ 60!

Figure 4-7: PSR Entry when Source can’t Send PSR Active SDP before Setup Time ..................................... 61!

Figure 4-8: PSR Exit Link Management With No Link Training ..................................................................... 63!

Figure 4-9: PSR Exit Link Management ........................................................................................................... 64!

Figure 4-10: PSR Entry Abort for Source TX Off Case .................................................................................... 65!

Figure 4-11: Single Frame Update Timing Shown with Optional SDP for PSR Exit ....................................... 67!

Figure 4-12: Burst Single Frame Update SDP Timing ...................................................................................... 67!

Figure 4-13: CRC SDP Timing with Frame Capture Indication = 0 and for Single Frame Update ................. 70!

Figure 4-14: CRC SDP Timing with Frame Capture Indication = 1 ................................................................. 70!

Figure 5-1: eDP Interface Power Up/Down Sequence, Normal System Operation ......................................... 71!

Figure 5-2: eDP Interface Power Up/Down Sequence, AUX Channel Transaction Only ............................... 71!

Figure 7-1: Example of VESA DisplayPort Panel Showing Warning Label Affixed Near Connector ........... 78!

Figure 7-2: Example of a DisplayPort Panel Warning Label ........................................................................... 78!

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