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Verilog-AMS实值建模指南.pdf
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实值建模(RVM)是一种方法,你可以通过它来执行模拟或验证 采用离散模拟实值的混合信号设计。 这只允许使用模拟 该数字解算器,避免了较慢的模拟仿真,实现了密集的验证 短时间内混合信号设计。 在这种情况下,您需要考虑权衡 在仿真性能和精度之间。 RVM还提供了链接的可能性 与其他先进的验证技术,如基于断言的验证,没有 与模拟引擎接口或定义新的语义来处理 模拟值。 预计您将通过迁移模拟来启用RVM flow 模型或晶体管级设计到RVM风格
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Verilog-AMS Real Valued Modeling Guide
Product Version 11.1
December 2011
© 2009-2011 Cadence Design Systems, Inc. All rights reserved.
Portions © Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation. Used by
permission.
Printed in the United States of America.
Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.
Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or
registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are
used with permission.
Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document
are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks,
contact the corporate legal department at the address shown above or call 800.862.4522. All other
trademarks are the property of their respective holders.
Restricted Permission: This publication is protected by copyright law and international treaties and
contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or
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customer.
2. The publication may not be modified in any way.
3. Any authorized copy of the publication or portion thereof must include all original copyright,
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software, whether for internal or external use, and shall not be used for the benefit of any other party,
whether or not for consideration.
Patents: Cadence Product described in this document, is protected by U.S. Patents
Disclaimer: Information in this publication is subject to change without notice and does not represent a
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usefulness of the information contained in this document. Cadence does not warrant that use of such
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Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth
in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor
Verilog-AMS Real Valued Modeling Guide
December 2011 3 Product Version 11.1
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Verification Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Real Value Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Simulation Performance, Accuracy, and Modeling Effort . . . . . . . . . . . . . . . . . . . . . . 11
Limitations of the RVM Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Model Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
A RVM-based Workflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Verilog-AMS Wreal Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Why wreal? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Verilog-AMS Wreal Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Advanced Wreal Modeling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Wreal Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Wreal X and Z State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multiple Driven Wreals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Wreal Coercion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Wreal Table Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Connecting Wreals to Other Domains and Languages
. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wreal connecting to VHDL real and SystemVerilog real . . . . . . . . . . . . . . . . . . . . . . 40
Connection to the Electrical Domain
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Connection to the Digital Domain
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Working with Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Discipline Naming
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Local Resolution Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Contents
Verilog-AMS Real Valued Modeling Guide
December 2011 4 Product Version 11.1
4
Modeling with Wreal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Sample Model Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
First Example: Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Analog Functions Translated to Wreal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Wreal Value Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Integration and Differentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Value Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Slew Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Modeling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Low Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Event-based and Fixed Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC/DAC Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5
Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6
Appendix A: Advanced Digital Verification Methodology . . . . 93
Verification Plan and Metric-driven Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Metric-driven Verification and Advanced Testbench
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7
Appendix B: Analog Simulation Today . . . . . . . . . . . . . . . . . . . . . . . . . 97
Mixed-signal Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Verilog-AMS Real Valued Modeling Guide
December 2011 5 Product Version 11.1
1
Introduction
Virtually all modern System on Chip (SoC) designs of today are mixed-signal designs. Mixed-
signal design is one of the biggest challenges of the modern sub-micron SoC design world.
Most systems have to interface their millions of gates, DSPs, memories, and processors to
the real world through a display, an antenna, a sensor, or a cable. This means that they have
analog and digital content. These mixed-signal SoCs have to be designed with an
unprecedented level of integration, in processes that have compromised every facet of
performance for size, and in a scale that exposes the designer to the ravages of physics of
small dimensions.
Until recently, mixed-signal designs could be decomposed into separate analog and digital
functions. Today, mixed-signal designs have multiple feedback loops through the analog and
digital domains. It is not practical to decompose them into separate functions without losing
essential system behavior. This requires an integrated mixed-signal simulation and
verification environment. Performance and reliability are now the key problems. Verification
has become the major bottleneck in the design flow.
The old way of using the tools will not work any more. It will take a lot of planning to figure out
a design and, even more important, a verification strategy before starting the effort. The tools
are much more capable than before, but the gap in solving analog types of problems in a pure
digital environment and vice versa is greater than ever. This requires a change in people’s
mentality, group structure, management, working style and obviously the tools chain, working
environment, and verification methodology.
Cadence has introduced a digital-centric mixed-signal verification environment – Digital
Mixed-signal (DMS). This new verification environment targets customers using digital-
centric use models. It refers to, but is not limited to, mixed-signal verification using only digital
simulators. In other words, it delivers capabilities to verify the mixed-signal design using
digital-centric methodologies. This book provides the overall benefits of the Digital-centric
Mixed-signal Verification methodology and explains how this methodology can enable
customers to perform top-level verification at digital speed.
The Verification Problem
chapter introduces the verification problem and highlights how real
value modeling can help overcome the current limitations. Appendix A: Advanced Digital
Verification Methodology and Appendix B: Analog Simulation Today provide additional
background information on the proposed methodology.
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