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RapidIO IP Core User Guide

Updated for Intel

Quartus

Prime Design Suite: 17.1

Send Feedback

UG-20078 | 2017.11.06

Latest document on the web: PDF | HTML

Contents

1 About the RapidIO IP Core...............................................................................................6

1.1 Features................................................................................................................7

1.1.1 Supported Transactions............................................................................... 8

1.2 Device Family Support.............................................................................................9

1.3 IP Core Verification................................................................................................. 9

1.3.1 Simulation Testing...................................................................................... 9

1.3.2 Hardware Testing...................................................................................... 10

1.3.3 Interoperability Testing.............................................................................. 11

1.4 Performance and Resource Utilization...................................................................... 11

1.5 Device Speed Grades............................................................................................ 13

1.6 Release Information.............................................................................................. 15

2 Getting Started.............................................................................................................. 17

2.1 Installing and Licensing Intel FPGA IP Cores............................................................. 17

2.1.1 Intel FPGA IP Evaluation Mode.................................................................... 18

2.2 Generating IP Cores.............................................................................................. 20

2.2.1 IP Core Generation Output (Intel Quartus Prime Pro Edition)...........................22

2.3 IP Core Generation Output (Intel Quartus Prime Standard Edition).............................. 24

2.4 RapidIO IP Core Testbench Files..............................................................................25

2.5 Simulating IP Cores..............................................................................................26

2.5.1 Simulating the Testbench with the ModelSim Simulator.................................. 26

2.5.2 Simulating the Testbench with the VCS Simulator..........................................27

2.6 Integrating Your IP Core in Your Design................................................................... 28

2.6.1 Calibration Clock.......................................................................................28

2.6.2 Dynamic Transceiver Reconfiguration Controller............................................ 28

2.6.3 Transceiver Settings.................................................................................. 29

2.6.4 Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix

IV GX Variations...................................................................................... 29

2.6.5 External Transceiver PLL............................................................................ 29

2.6.6 Transceiver PHY Reset Controller for Intel Arria 10 Variations.......................... 31

2.7 Specifying Timing Constraints.................................................................................31

2.8 Compiling the Full Design and Programming the FPGA............................................... 33

2.9 Instantiating Multiple RapidIO IP Cores.................................................................... 33

2.9.1 Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations..33

2.9.2 Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX,

and Stratix IV GX Variations...................................................................... 35

2.9.3 Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP

Core Instances........................................................................................ 35

2.9.4 Sourcing Multiple Tcl Scripts for Variations other than Intel Arria 10 ................ 35

3 Parameter Settings........................................................................................................ 37

3.1 Physical Layer Settings.......................................................................................... 37

3.1.1 Device Options......................................................................................... 37

3.1.2 Data Settings........................................................................................... 38

3.1.3 Receive Priority Retry Thresholds................................................................ 39

3.1.4 Transceiver Settings.................................................................................. 40

3.2 Transport and Maintenance Settings........................................................................ 40

3.2.1 Transport Layer........................................................................................ 40

Contents

RapidIO IP Core User Guide

3.2.2 Input/Output Maintenance Logical Layer Module............................................41

3.2.3 Port Write................................................................................................ 42

3.3 I/O and Doorbell Settings.......................................................................................42

3.3.1 I/O Logical Layer Interfaces........................................................................43

3.3.2 I/O Slave Address Width............................................................................ 43

3.3.3 I/O Read and Write Order Preservation........................................................ 43

3.3.4 Avalon-MM Master.....................................................................................43

3.3.5 Avalon-MM Slave...................................................................................... 44

3.3.6 Doorbell Slave.......................................................................................... 44

3.4 Capability Registers Settings.................................................................................. 44

3.4.1 Device Registers....................................................................................... 44

3.4.2 Assembly Registers................................................................................... 45

3.4.3 Processing Element Features...................................................................... 46

3.4.4 Switch Support......................................................................................... 46

3.4.5 Data Messages......................................................................................... 47

4 Functional Description................................................................................................... 48

4.1 Interfaces............................................................................................................ 48

4.1.1 RapidIO Interface......................................................................................48

4.1.2 Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces...................48

4.1.3 Avalon Streaming (Avalon-ST) Interface.......................................................49

4.2 Clocking and Reset Structure..................................................................................50

4.2.1 RapidIO IP Core Clocking........................................................................... 50

4.2.2 Reset for RapidIO IP Cores......................................................................... 54

4.3 Physical Layer...................................................................................................... 57

4.3.1 Features.................................................................................................. 57

4.3.2 Physical Layer Architecture.........................................................................58

4.3.3 Low-level Interface Receiver.......................................................................59

4.3.4 Low-Level Interface Transmitter.................................................................. 60

4.3.5 Protocol and Flow Control Engine................................................................ 61

4.3.6 Physical Layer Receive Buffer......................................................................61

4.3.7 Physical Layer Transmit Buffer.................................................................... 64

4.4 Transport Layer.................................................................................................... 67

4.4.1 Receiver.................................................................................................. 68

4.4.2 Transaction ID Ranges............................................................................... 69

4.4.3 Transmitter.............................................................................................. 69

4.5 Logical Layer Modules............................................................................................70

4.5.1 Concentrator Register Module..................................................................... 70

4.5.2 Maintenance Module..................................................................................73

4.5.3 Input/Output Logical Layer Modules.............................................................82

4.5.4 Doorbell Module...................................................................................... 102

4.5.5 Avalon-ST Pass-Through Interface............................................................. 106

4.6 Error Detection and Management.......................................................................... 111

4.6.1 Physical Layer Error Management.............................................................. 111

4.6.2 Logical Layer Error Management............................................................... 113

4.6.3 Avalon-ST Pass-Through Interface............................................................. 118

5 Signals......................................................................................................................... 119

5.1 Physical Layer Signals..........................................................................................119

5.1.1 Status Packet and Error Monitoring Signals................................................. 121

5.1.2 Multicast Event Signals............................................................................ 122

Contents

RapidIO IP Core User Guide

5.1.3 Receive Priority Retry Threshold-Related Signals..........................................122

5.1.4 Physical Layer Buffer Status Signals...........................................................123

5.1.5 Transceiver Signals..................................................................................123

5.1.6 Register-Related Signals...........................................................................128

5.2 Transport and Logical Layer Signals....................................................................... 129

5.2.1 Avalon-MM Interface Signals.....................................................................129

5.2.2 Avalon-ST Pass-Through Interface Signals.................................................. 132

5.2.3 Error Management Extension Signals......................................................... 134

5.2.4 Packet and Error Monitoring Signal for the Transport Layer............................136

6 Software Interface.......................................................................................................137

6.1 Physical Layer Registers.......................................................................................141

6.2 Transport and Logical Layer Registers.................................................................... 147

6.2.1 Capability Registers (CARs)...................................................................... 147

6.2.2 Command and Status Registers (CSRs)...................................................... 151

6.2.3 Maintenance Interrupt Control Registers.....................................................152

6.2.4 Receive Maintenance Registers..................................................................153

6.2.5 Transmit Maintenance Registers................................................................ 153

6.2.6 Transmit Port-Write Registers....................................................................154

6.2.7 Receive Port-Write Registers..................................................................... 155

6.2.8 Input/Output Master Address Mapping Registers..........................................155

6.2.9 Input/Output Slave Mapping Registers....................................................... 156

6.2.10 Input/Output Slave Interrupts.................................................................158

6.2.11 Transport Layer Feature Register............................................................. 159

6.2.12 Error Management Registers................................................................... 160

6.2.13 Doorbell Message Registers.....................................................................162

7 Testbench.................................................................................................................... 166

7.1 Reset, Initialization, and Configuration................................................................... 168

7.2 Maintenance Write and Read Transactions...............................................................170

7.3 SWRITE Transactions...........................................................................................171

7.4 NWRITE_R Transactions....................................................................................... 171

7.5 NWRITE Transactions...........................................................................................172

7.6 NREAD Transactions............................................................................................ 173

7.7 Doorbell Transactions...........................................................................................174

7.8 Doorbell and Write Transactions With Transaction Order Preservation......................... 174

7.9 Port-Write Transactions........................................................................................ 176

7.10 Transactions Across the Avalon-ST Pass-Through Interface...................................... 177

8 Platform Designer (Standard) Design Example............................................................ 178

8.1 Creating a New Intel Quartus Prime Project............................................................ 180

8.2 Running Platform Designer (Standard)................................................................... 180

8.2.1 Adding and Parameterizing the RapidIO Component.....................................181

8.2.2 Adding and Connecting Other System Components...................................... 183

8.2.3 Connecting Clocks and the System Components.......................................... 185

8.2.4 Generating the System............................................................................ 188

8.3 Simulating the System.........................................................................................188

A Initialization Sequence................................................................................................ 190

B Porting a RapidIO Design from the Previous Version of Software................................ 192

B.1 Upgrading a RapidIO Design Without Changing Device Family................................... 192

Contents

RapidIO IP Core User Guide

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