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JEDEC Standard No. 21C
Page 4.20.19-1
Revision 1.06 Release 22A
4.20.19 - 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000
DDR3 SDRAM Unbuffered DIMM Design Specification
DDR3 SDRAM Unbuffered DIMM Design Specification
Revision 1.06
January 2013
Release 22A Revision 1.06
JEDED Standard No. 21C
Page 4.20.19-2
This page left blank
JEDEC Standard No. 21C
Page 4.20.19-3
Revision 1.06 Release 22A
Table of Contents
1 Product Description .............................................................................................................9
2 Environmental Requirements ...........................................................................................10
3 Architecture ........................................................................................................................11
3.1 Address Mirroring Feature .................................................................................................. 16
4 Component Details .............................................................................................................25
5 Unbuffered DIMM Details ................................................................................................27
5.1 DDR3 Unbuffered Design File Releases .............................................................................. 28
5.2 Component Types and Placement........................................................................................ 29
5.3 Decoupling Guidelines........................................................................................................... 33
6 DIMM Wiring Details ........................................................................................................35
6.1 Signal Groups......................................................................................................................... 35
6.2 General Net Structure Routing Rules.................................................................................. 35
6.2.1 Clock, Control, and Address/Command Groups ..........................................................................35
6.2.2 Lead-in vs. Loaded Sections.........................................................................................................36
6.2.3 Length/Delay Matching to SDRAM Devices...............................................................................36
6.2.4 Velocity Compensation ................................................................................................................37
6.2.5 Load/Delay Compensation ...........................................................................................................37
6.2.6 Data and Strobe Group .................................................................................................................37
6.2.7 Via Compensation ........................................................................................................................37
6.3 Explanation of Net Structure Diagrams .............................................................................. 37
6.4 Clock Net Structures ............................................................................................................. 39
6.5 Net Structure Routing for Control....................................................................................... 45
6.6 Net Structure Routing for Address/Command................................................................... 49
6.7 Net Structure Routing for Data............................................................................................ 53
6.8 Cross Section Recommendations.......................................................................................... 70
6.9 Test Point Identification........................................................................................................ 74
7 Serial Presence Detect ........................................................................................................86
7.1 Serial Presence Detect Component Specification ............................................................... 86
7.2 Serial Presence Detect Definition ......................................................................................... 86
8 Product Label .....................................................................................................................88
9 DIMM Mechanical Specifications.....................................................................................90
Release 22A Revision 1.06
JEDED Standard No. 21C
Page 4.20.19-4
Figures
Figure 1 —Wiring Differences for Mirrored and Non-Mirrored Addresses .................................... 17
Figure 2 —Block Diagram: Raw Card Version A, x64.................................................................... 18
Figure 3 —Block Diagram: Raw Card Version B, x64 .................................................................... 19
Figure 4 —Block Diagram: Raw Card Version C, x64 .................................................................... 20
Figure 5 —Block Diagram: Raw Card Version D and J, x72 .......................................................... 21
Figure 6 —Block Diagram: Raw Card Version E and K, x72.......................................................... 22
Figure 7 —Block Diagram: Raw Card Version F, x64 .................................................................... 23
Figure 8 —Block Diagram: SPD and Thermal Sensor for Raw Cards D, E, J and K ...................... 24
Figure 9 —DIMM Ball Pattern for x8 - 512Mb, 1Gb, 2Gb, 4Gb, and 8Gb
DDR3 SDRAM Planar Components (Top View)......................................................... 25
Figure 10 —DIMM Ball Pattern for x16 - 512Mb, 1Gb, 2Gb, 4Gb, and 8Gb DDR3 SDRAM Planar
Components (Top View)............................................................................................... 26
Figure 11 —Example Component Placement (Raw Card Version A) ............................................. 29
Figure 12 —Example Component Placement (Raw Card Version B) ............................................. 29
Figure 13 —Example Component Placement (Raw Card Version C) ............................................. 30
Figure 14 —Example Component Placement (Raw Card Version D) ............................................. 30
Figure 15 —Example Component Placement (Raw Card Version E).............................................. 31
Figure 16 —Example Component Placement (Raw Card Version F).............................................. 31
Figure 17 —Example Component Placement (Raw Card Version J)............................................... 32
Figure 18 —Example Component Placement (Raw Card Version K) ............................................. 32
Figure 19 —Fly-By Topology .......................................................................................................... 34
Figure 20—Net Structure Example .................................................................................................. 38
Figure 21—Clock Net Structures (Raw Card Version A) CK0_t, CK0_c ....................................... 39
Figure 22 —Clock Net Structures (Raw Card Version B) CK0_t, CK0_c, CK1_t, CK1_c ............ 40
Figure 23 —Clock Net Structures (Raw Card Version C) CK0_t, CK0_c ...................................... 41
Figure 24 —Clock Net Structures (Raw Card Version D and J) CK0_t, CK0_c............................. 42
Figure 25 —Clock Net Structures (Raw Card Version E and K) CK0_t, CK0_c, CK1_t, CK1_c .. 43
Figure 26 —Clock Net Structures (Raw Card Version F) CK0_t, CK0_c, CK1_t, CK1_c............. 44
Figure 27 —Net Structure Routing for Control (Raw Card Version A)
S0_n, ODT0 and CKE0 ................................................................................................ 45
Figure 28 —Net Structure Routing for Control (Raw Card Version B)
S0_n, S1_n, ODT0, ODT1, CKE0, and CKE1............................................................. 45
Figure 29 —Net Structure Routing for Control (Raw Card Version C)
S0_n, ODT0 and CKE0 ................................................................................................ 46
Figure 30—Net Structure Routing for Control (Raw Card Version D and J)
S0_n, ODT0 and CKE0 ................................................................................................ 46
Figure 31—Net Structure Routing for Control (Raw Card Version E and K)
S0_n, S1_n, ODT0, ODT1, CKE0, CKE1.................................................................... 47
Figure 32 —Net Structure Routing for Control (Raw Card Version F)
S0_n, S1_n, ODT0, ODT1, CKE0, CKE1.................................................................... 48
Figure 33 —Net Structure Routing for Address and Command (Raw Card Version A) ................. 49
Figure 34 —Net Structure Routing for Address and Command (Raw Card Version B).................. 49
Figure 35 —Net Structure Routing for Address and Command (Raw Card Version C).................. 50
Figure 36 —Net Structure Routing for Address and Command (Raw Card Version D and J)........ 50
JEDEC Standard No. 21C
Page 4.20.19-5
Revision 1.06 Release 22A
FiguresFigures
Figure 37 —Net Structure Routing for Address and Command (Raw Card Version E and K)........51
Figure 38 —Net Structure Routing for Address and Command (Raw Card Version F)...................52
Figure 39 —Net Structure Routing for Data (Raw Card Version A)
DQ/DM and DQS_t/DQS_c ..........................................................................................53
Figure 40—Net Structure Routing for Data (Raw Card Version B)
DQ/DM and DQS_t/DQS_c ..........................................................................................55
Figure 41—Net Structure Routing for Data (Raw Card Version C)
DQ/DM and DQS_t/DQS_c ..........................................................................................57
Figure 42 —Net Structure Routing for Data (Raw Card Version D)
DQ/DM and DQS_t/DQS_c ..........................................................................................59
Figure 43 —Net Structure Routing for Data (Raw Card Version E)
DQ/DM and DQS_t/DQS_c ..........................................................................................61
Figure 44 —Net Structure Routing for Data (Raw Card Version F)
DQ/DM and DQS_t/DQS_c ..........................................................................................64
Figure 45 —Net Structure Routing for Data (Raw Card Version J)
DQ/DM and DQS_t/DQS_c ..........................................................................................66
Figure 46 —Net Structure Routing for Data (Raw Card Version K)
DQ/DM and DQS_t/DQS_c ..........................................................................................68
Figure 47 —Six-Layer Stackup (Example) .......................................................................................71
Figure 48 —Eight-Layer Stackup (Example)....................................................................................73
Figure 49 —Test Point Identification (Raw Card Version A): Back View.......................................74
Figure 50 —Test Point Identification (Raw Card Version A): Bottom View ...................................74
Figure 51 —Test Point Identification (Raw Card Version B): Front View, Left Side......................75
Figure 52 —Test Point Identification (Raw Card Version B): Front View, Right Side....................75
Figure 53 —Test Point Identification (Raw Card C): Backside View
The Address and Command, Control, and Clock Structure Pins...................................76
Figure 54 —Raw Card C Test Points (Raw Card C): The Termination Resistors ............................77
Figure 55 —Test Point Identification (Raw Card C): Backside View, The DQ Group ....................77
Figure 56 —Test Point Identification (Raw Card Version D): Front Side, Full Board View ...........78
Figure 57 —Test Point Identification (Raw Card Version D): Front Side, Detailed View...............78
Figure 58 —Test Point Identification (Raw Card Version D): Back Side, Full Board View ...........78
Figure 59 —Test Point Identification (Raw Card Version D): Back Side View
Test Point Area at the Terminations ..............................................................................79
Figure 60 —Test Point Identification (Raw Card Version D): Back Side View
Test Point Area Under the DRAMs...............................................................................79
Figure 61 —Test Point Identification (Raw Card Version D): Back Side View
Termination Area at the First DRAM............................................................................79
Figure 62 —Test Point Identification (Raw Card Version E): Front Side View, Full Board ...........80
Figure 63 —Test Point Identification (Raw Card Version E): Front Side View
Test Points Near the First DRAM..................................................................................80
Figure 64 —Test Point Identification (Raw Card Version E): Front Side View
Test Points Between the Fifth and Sixth DRAM Sites..................................................81
Figure 65 —Test Point Identification (Raw Card Version E): Front Side View
Test Points at the Terminations .....................................................................................81
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