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5-Jan-2012
Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
MIPI
®
Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011
* NOTE TO IMPLEMENTERS *
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to
this MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
However, implementers should be aware of the following:
It is the good faith expectation of the MIPI PHY Working Group that D-PHY v1.1 is stable and
robust. The MIPI Alliance currently recommends that any member companies considering
implementation of D-PHY base their work on this version of the Specification (v1.1), which is
intended to supersede the previous version (v1.00.00).
This version of the Specification includes minor relaxations to the conformance ranges for several
key parameters. These modifications are intended to ease implementation for designs supporting
HS bitrates > 1 Gbps, allowing for slightly greater conformance margins for these parameters, to
better allow for process and manufacturing variations in these implementations.
In some cases the modified conformance limits apply only to operation at HS rates > 1 Gbps
(while the previous limits still apply to rates ≤ 1Gbps), while in other cases the new conformance
values are applicable to all HS rates. In all cases, the modified conformance limits have been
widened with respect to the previous values, so that any implementation conformant to these
parameters in the previous version of this Specification (v1.00.00) should also be conformant to
the modified limits defined in this version (v1.1).
The follow list includes all parameters with modified conformance limits:
• HS rise/fall time (t
R
, t
F
)
• VOD mismatch (ΔV
OD
)
• TX data to clock skew (T
SKEW[TX]
)
• RX setup and hold times (T
SETUP[RX]
, T
HOLD[RX]
)
• TX and RX return loss (Sdd
TX
, Sdd
RX
)

5-Jan-2012
Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
See the respective Specification sections for details.
Also in this version of the Specification, one new parameter has been added (∆UI) that more
precisely constrains the allowed peak-to-peak variation of the HS bitrate (UI) within a single HS
burst. The addition of this new parameter is intended to address suspected interoperability
concerns that may arise for devices that show excessive variability of their HS-TX bitrate within a
single HS burst.
It is the good faith expectation of the MIPI PHY WG that there will be no significant functional
changes to the fundamental technology described in this Specification.

Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
MIPI
®
Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011
MIPI Board Approved 16-Dec-2011
Further technical changes to this document are expected as work continues in the PHY Working Group

Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
ii
NOTICE OF DISCLAIMER 1
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or 2
controlled by any of the authors or developers of this material or MIPI
®
. The material contained herein is 3
provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is 4
provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI 5
hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not 6
limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a 7
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of 8
viruses, and of lack of negligence. 9
All materials contained herein are protected by copyright laws, and may not be reproduced, republished, 10
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express 11
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all 12
related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI 13
Alliance and cannot be used without its express prior written permission. 14
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET 15
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 16
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY 17
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 18
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE 19
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 20
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER 21
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR 22
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, 23
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH 24
DAMAGES. 25
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document 26
is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of 27
the contents of this Document; (b) does not monitor or enforce compliance with the contents of this 28
Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of 29
compliance with the contents of this Document. The use or implementation of the contents of this 30
Document may involve or require the use of intellectual property rights ("IPR") including (but not limited 31
to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of 32
MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the 33
disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. 34
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 35
MIPI Alliance, Inc. 36
c/o IEEE-ISTO 37
445 Hoes Lane 38
Piscataway, NJ 08854 39
Attn: Board Secretary 40

Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iii
Contents 41
Version 1.1 – 7 November 2011 ................................................................................................................ i
42
1
Introduction .................................................................................................................................... 10 43
1.1
Scope ...................................................................................................................................... 10 44
1.2
Purpose ................................................................................................................................... 11 45
2
Terminology ................................................................................................................................... 12 46
2.1
Definitions .............................................................................................................................. 12 47
2.2
Abbreviations .......................................................................................................................... 13 48
2.3
Acronyms ............................................................................................................................... 13 49
3
References ...................................................................................................................................... 16 50
4
D-PHY Overview ............................................................................................................................ 17 51
4.1
Summary of PHY Functionality............................................................................................... 17 52
4.2
Mandatory Functionality ......................................................................................................... 17 53
5
Architecture .................................................................................................................................... 18
54
5.1
Lane Modules ......................................................................................................................... 18 55
5.2
Master and Slave..................................................................................................................... 19 56
5.3
High Frequency Clock Generation........................................................................................... 19
57
5.4
Clock Lane, Data Lanes and the PHY-Protocol Interface ......................................................... 19 58
5.5
Selectable Lane Options .......................................................................................................... 20 59
5.6
Lane Module Types ................................................................................................................. 22
60
5.6.1
Unidirectional Data Lane ................................................................................................. 23 61
5.6.2
Bi-directional Data Lanes ................................................................................................ 23 62
5.6.3
Clock Lane ...................................................................................................................... 24 63
5.7
Configurations ........................................................................................................................ 24 64
5.7.1
Unidirectional Configurations.......................................................................................... 26 65
5.7.2
Bi-Directional Half-Duplex Configurations...................................................................... 28 66
5.7.3
Mixed Data Lane Configurations ..................................................................................... 29 67
6
Global Operation ............................................................................................................................ 30 68
6.1
Transmission Data Structure ................................................................................................... 30 69
6.1.1
Data Units ....................................................................................................................... 30 70
6.1.2
Bit order, Serialization, and De-Serialization ................................................................... 30 71
6.1.3
Encoding and Decoding ................................................................................................... 30 72
6.1.4
Data Buffering ................................................................................................................. 30 73
6.2
Lane States and Line Levels .................................................................................................... 30 74
6.3
Operating Modes: Control, High-Speed, and Escape ............................................................... 31 75
6.4
High-Speed Data Transmission ............................................................................................... 32 76
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