loginid=molbasic01@ginreen.com,time=2018-05-30 11:16:48,ip=113.116.51.226,doctitle=MT6761 LTE-A Smartphone Application Processor Technical Brief V1.0.pdf,company=Ginreen_WCX
MT6761
LTE-A Smartphone Application Processor
Technical Brief
Confidential A
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Figure 2-20. MSDC output timing diagram of variable window (SDR104) .............................................47
Figure 2-21. MSDC clock timing diagram of DDR50 speed mode .......................................................... 48
Figure 2-22. MSDC input/output timing diagram of DDR50 speed mode ............................................. 49
Figure 2-23. MSDC clock timing diagram of HS200 ............................................................................... 50
Figure 2-24. MSDC input timing diagram of HS200 ............................................................................... 50
Figure 2-25. MSDC output timing diagram of HS200 ............................................................................. 50
Figure 2-26. MSDC input timing diagram of HS400 ................................................................................ 51
Figure 2-27. MSDC output timing diagram of HS400 ............................................................................. 52
Figure 2-28. Power on sequence ................................................................................................................. 55
Figure 2-29. Block diagram of BBRX-ADC ................................................................................................ 57
Figure 2-30. Block diagram of BBTX ........................................................................................................ 59
Figure 2-31. Block diagram of ETDAC ...................................................................................................... 60
Figure 2-32. Block diagram of DETADC .................................................................................................... 61
Figure 2-33. Block diagram of APC-DAC .................................................................................................. 62
Figure 2-34. Outlines and dimensions of VFBGA 11.4mm*11mm, 558-ball, 0.4mm pitch package ..... 65
Figure 2-35. Top marking of MT6761 .........................................................................................................67
Table 2-1. Pin coordinate ............................................................................................................................ 18
Table 2-2. Acronym for pin type ................................................................................................................. 21
Table 2-3. Detailed pin description ........................................................................................................... 22
Table 2-4. Acronym for table of state of pins ............................................................................................ 32
Table 2-5. Absolute maximum ratings for power supply ......................................................................... 33
Table 2-6. Recommended operating conditions for power supply .......................................................... 34
Table 2-7. RTC DC electrical characteristics (DVDD18_IOLT =1.8V) .................................................... 35
Table 2-8. SPI, I2S DC electrical characteristics (DVDD18_IORB =1.8V) ............................................. 35
Table 2-9. I2C0, I2C1, I2C2 DC electrical characteristics (DVDD18_IORB =1.8V) ............................... 36
Table 2-10. I2C3 DC electrical characteristics (DVDD18_IOLB =1.8V) ................................................. 36
Table 2-11. MSDC0 DC electrical characteristics (DVDD28_MSDC0=1.8V) ......................................... 36
Table 2-12. MSDC1 DC electrical characteristics (DVDD28_MSDC1=2.8V/3.3V) ................................ 36
Table 2-13. MSDC1 DC electrical characteristics (DVDD28_MSDC1=1.8V) ........................................... 37
Table 2-14. SIM DC electrical characteristics ............................................................................................ 37
Table 2-15. LPDDR3 AC timing parameter table of external memory interface .................................... 40
Table 2-16. LPDDR4X AC timing parameter table of external memory interface .................................. 41
Table 2-17. SPI AC timing parameters ...................................................................................................... 42
Table 2-18. I2S AC timing parameters ...................................................................................................... 42
Table 2-19. I2C AC timing parameters ...................................................................................................... 43
Table 2-20. MSDC AC timing parameters of default speed ..................................................................... 45
Table 2-21. MSDC AC timing parameters of high speed .......................................................................... 46
Table 2-22. MSDC AC timing parameters of SDR12/SDR25/SDR50/SDR104 mode ............................47
Table 2-23. MSDC AC timing parameters of DDR50 speed mode .......................................................... 49
Table 2-24. MSDC AC timing parameters of HS200 ................................................................................. 51
Table 2-25. MSDC AC timing parameters of HS400 ................................................................................ 52
Table 2-26. SIM AC timing parameters .................................................................................................... 53
Table 2-27. Mode selection ........................................................................................................................ 54
Table 2-28. Constant tied pins ................................................................................................................... 54
Table 2-29. Baseband downlink specifications ......................................................................................... 58
Table 2-30. BBTX specifications................................................................................................................ 59
Table 2-31. ETDAC specifications .............................................................................................................. 60
Table 2-32. DETADC specifications ........................................................................................................... 61
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