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ARM Cortex-A53 MPCore开发手册
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ARM Cortex-A53 MPCore开发手册,ARM Cortex-A53 MPCore开发手册。
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Copyright © 2013-2014 ARM. All rights reserved.
ARM DDI 0500F (ID080114)
ARM
®
Cortex
®
-A53 MPCore Processor
Revision: r0p4
Technical Reference Manual
ARM DDI 0500F Copyright © 2013-2014 ARM. All rights reserved. ii
ID080114 Non-Confidential
ARM Cortex-A53 MPCore Processor
Technical Reference Manual
Copyright © 2013-2014 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM
®
in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
09 August 2013 A Confidential Release for r0p0
05 November 2013 B Confidential Release for r0p1
10 January 2014 C Confidential Release for r0p2
14 February 2014 D Non-Confidential Second release for r0p2
30 April 2014 E Non-Confidential Release for r0p3
29 July 2014 F Non-Confidential Release for r0p4
ARM DDI 0500F Copyright © 2013-2014 ARM. All rights reserved. iii
ID080114 Non-Confidential
Contents
ARM Cortex-A53 MPCore Processor Technical
Reference Manual
Preface
About this book .......................................................................................................... vii
Feedback .................................................................................................................... xi
Chapter 1 Introduction
1.1 About the Cortex-A53 processor ............................................................................. 1-2
1.2 Compliance .............................................................................................................. 1-3
1.3 Features ................................................................................................................... 1-5
1.4 Interfaces ................................................................................................................. 1-6
1.5 Implementation options ............................................................................................ 1-7
1.6 Test features ............................................................................................................ 1-9
1.7 Product documentation and design flow ................................................................ 1-10
1.8 Product revisions ................................................................................................... 1-12
Chapter 2 Functional Description
2.1 About the Cortex-A53 processor functions .............................................................. 2-2
2.2 Interfaces ................................................................................................................. 2-7
2.3 Clocking and resets ................................................................................................. 2-9
2.4 Power management ............................................................................................... 2-16
Chapter 3 Programmers Model
3.1 About the programmers model ................................................................................ 3-2
3.2 ARMv8-A architecture concepts .............................................................................. 3-4
Chapter 4 System Control
4.1 About system control ............................................................................................... 4-2
Contents
ARM DDI 0500F Copyright © 2013-2014 ARM. All rights reserved. iv
ID080114 Non-Confidential
4.2 AArch64 register summary ...................................................................................... 4-3
4.3 AArch64 register descriptions ................................................................................ 4-16
4.4 AArch32 register summary .................................................................................. 4-126
4.5 AArch32 register descriptions .............................................................................. 4-149
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................................ 5-2
5.2 TLB organization ...................................................................................................... 5-3
5.3 TLB match process .................................................................................................. 5-4
5.4 External aborts ......................................................................................................... 5-5
Chapter 6 Level 1 Memory System
6.1 About the L1 memory system .................................................................................. 6-2
6.2 Cache behavior ........................................................................................................ 6-3
6.3 Support for v8 memory types ................................................................................... 6-6
6.4 L1 Instruction memory system ................................................................................. 6-7
6.5 L1 Data memory system .......................................................................................... 6-9
6.6 Data prefetching .................................................................................................... 6-12
6.7 Direct access to internal memory .......................................................................... 6-13
Chapter 7 Level 2 Memory System
7.1 About the L2 memory system .................................................................................. 7-2
7.2 Snoop Control Unit .................................................................................................. 7-3
7.3 ACE master interface ............................................................................................... 7-6
7.4 CHI master interface .............................................................................................. 7-13
7.5 Additional memory attributes ................................................................................. 7-17
7.6 Optional integrated L2 cache ................................................................................. 7-18
7.7 ACP ....................................................................................................................... 7-19
Chapter 8 Cache Protection
8.1 Cache protection behavior ....................................................................................... 8-2
8.2 Error reporting .......................................................................................................... 8-4
8.3 Error injection ........................................................................................................... 8-5
Chapter 9 Generic Interrupt Controller CPU Interface
9.1 About the GIC CPU Interface .................................................................................. 9-2
9.2 GIC programmers model ......................................................................................... 9-3
Chapter 10 Generic Timer
10.1 About the Generic Timer ........................................................................................ 10-2
10.2 Generic Timer functional description ..................................................................... 10-3
10.3 Generic Timer register summary ........................................................................... 10-4
Chapter 11 Debug
11.1 About debug .......................................................................................................... 11-2
11.2 Debug register interfaces ....................................................................................... 11-4
11.3 AArch64 debug register summary ......................................................................... 11-6
11.4 AArch64 debug register descriptions ..................................................................... 11-8
11.5 AArch32 debug register summary ....................................................................... 11-14
11.6 AArch32 debug register descriptions ................................................................... 11-16
11.7 Memory-mapped register summary ..................................................................... 11-20
11.8 Memory-mapped register descriptions ................................................................ 11-24
11.9 Debug events ....................................................................................................... 11-36
11.10 External debug interface ...................................................................................... 11-37
11.11 ROM table ............................................................................................................ 11-41
Chapter 12 Performance Monitor Unit
12.1 About the PMU ...................................................................................................... 12-2
Contents
ARM DDI 0500F Copyright © 2013-2014 ARM. All rights reserved. v
ID080114 Non-Confidential
12.2 PMU functional description .................................................................................... 12-3
12.3 AArch64 PMU register summary ........................................................................... 12-5
12.4 AArch64 PMU register descriptions ....................................................................... 12-7
12.5 AArch32 PMU register summary ......................................................................... 12-14
12.6 AArch32 PMU register descriptions ..................................................................... 12-16
12.7 Memory-mapped register summary ..................................................................... 12-23
12.8 Memory-mapped register descriptions ................................................................ 12-26
12.9 Events .................................................................................................................. 12-36
12.10 Interrupts .............................................................................................................. 12-40
12.11 Exporting PMU events ......................................................................................... 12-41
Chapter 13 Embedded Trace Macrocell
13.1 About the ETM ....................................................................................................... 13-2
13.2 ETM trace unit generation options and resources ................................................. 13-3
13.3 ETM trace unit functional description ..................................................................... 13-5
13.4 Reset ..................................................................................................................... 13-7
13.5 Modes of operation and execution ......................................................................... 13-8
13.6 ETM trace unit register interfaces .......................................................................... 13-9
13.7 ETM register summary ........................................................................................ 13-10
13.8 ETM register descriptions .................................................................................... 13-13
13.9 Interaction with debug and performance monitoring unit ..................................... 13-76
Chapter 14 Cross Trigger
14.1 About the cross trigger ........................................................................................... 14-2
14.2 Trigger inputs and outputs ..................................................................................... 14-3
14.3 Cortex-A53 CTM .................................................................................................... 14-4
14.4 Cross trigger register summary ............................................................................. 14-5
14.5 Cross trigger register descriptions ......................................................................... 14-8
Appendix A Signal Descriptions
A.1 About the signal descriptions ................................................................................... A-2
A.2 Clock signals ............................................................................................................ A-3
A.3 Reset signals ........................................................................................................... A-4
A.4 Configuration signals ............................................................................................... A-5
A.5 Generic Interrupt Controller signals ......................................................................... A-6
A.6 Generic Timer signals .............................................................................................. A-8
A.7 Power management signals .................................................................................... A-9
A.8 L2 error signals ...................................................................................................... A-11
A.9 ACE and CHI interface signals .............................................................................. A-12
A.10 CHI interface signals .............................................................................................. A-13
A.11 ACE interface signals ............................................................................................ A-17
A.12 ACP interface signals ............................................................................................ A-22
A.13 External debug interface ........................................................................................ A-25
A.14 ATB interface signals ............................................................................................. A-28
A.15 Miscellaneous ETM trace unit signals ................................................................... A-29
A.16 CTI interface signals .............................................................................................. A-30
A.17 PMU interface signals ............................................................................................ A-31
A.18 DFT and MBIST interface signals .......................................................................... A-32
Appendix B Cortex-A53 Processor AArch32 unpredictable Behaviors
B.1 Use of R15 by Instruction ........................................................................................ B-3
B.2 unpredictable instructions within an IT Block ........................................................... B-4
B.3 Load/Store accesses crossing page boundaries ..................................................... B-5
B.4 ARMv8 Debug unpredictable behaviors .................................................................. B-6
B.5 Other unpredictable behaviors ............................................................................... B-11
Appendix C Revisions
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