RTL8306E-CG_Realtek.pdf_rtl8306e

RTL8305SD

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RTL8306E-CG

SINGLE-CHIP 6-PORT 10/100MBPS

ETHERNET SWITCH CONTROLLER WITH

DUAL MII/RMII INTERFACES

DATASHEET

(CONFIDENTIAL: Development Partners Only)

Rev. 1.1

03 November 2010

Track ID: JATR-2265-11

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan

Tel.: +886-3-578-0211. Fax: +886-3-577-6047

www.realtek.com

RTL8306E

Datasheet

Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller

with Dual MII/RMII Interfaces

iii Track ID: JATR-2265-11 Rev. 1.1

Table of Contents

GENERAL DESCRIPTION..............................................................................................................................................1

FEATURES.........................................................................................................................................................................3

SYSTEM APPLICATIONS...............................................................................................................................................4

BLOCK DIAGRAM...........................................................................................................................................................5

PIN ASSIGNMENTS .........................................................................................................................................................6

5.1.

SSIGNMENTS

IAGRAM

.......................................................................................................................................6

5.2.

ACKAGE

DENTIFICATION

...........................................................................................................................................6

5.3.

SSIGNMENTS

ABLE

............................................................................................................................................7

PIN DESCRIPTIONS.........................................................................................................................................................9

6.1.

EDIA

ONNECTION

INS

...........................................................................................................................................9

6.2.

ODE

ONFIGURATION

INS

.......................................................................................................................................9

6.3.

ORT

MAC

IRCUIT

NTERFACE

INS

......................................................................................................................13

6.4.

ORT

PHY

IRCUIT

NTERFACE

INS

......................................................................................................................16

6.5.

ISCELLANEOUS

INS

...............................................................................................................................................20

6.6.

ORT

LED

INS

.........................................................................................................................................................21

6.7.

ERIAL

EEPROM

AND

SMI

INS

..............................................................................................................................23

6.8.

TRAPPING

INS

.........................................................................................................................................................24

6.9.

ORT

TATUS

TRAPPING

INS

..................................................................................................................................26

6.10.

OWER

INS

...............................................................................................................................................................27

BASIC FUNCTIONAL DESCRIPTION........................................................................................................................28

7.1.

WITCH

ORE

UNCTION

VERVIEW

.........................................................................................................................28

7.1.1.

Dual MII/RMII .....................................................................................................................................................28

7.1.1.1

Description....................................................................................................................................................................28

7.1.1.2 Dual MII/RMII Mode Configuration............................................................................................................................29

7.1.1.3

Port4 (5th Port) and Port5 (6th MAC) Status Configuration.........................................................................................30

7.1.2.

Port0, 1, 2, 3 Status Configuration.......................................................................................................................30

7.1.3.

Flow Control ........................................................................................................................................................31

7.1.3.1

IEEE 802.3x Full Duplex Flow Control........................................................................................................................31

7.1.3.2 Force Mode Full Duplex Flow Control.........................................................................................................................31

7.1.3.3

Half Duplex Back Pressure...........................................................................................................................................31

7.1.3.4 NWay Mode..................................................................................................................................................................31

7.1.3.5

Force Mode...................................................................................................................................................................32

7.1.4.

Address Search, Learning, and Aging ..................................................................................................................32

7.1.5.

Half Duplex Operation .........................................................................................................................................32

7.1.6.

InterFrame Gap....................................................................................................................................................33

7.1.7.

Illegal Frame........................................................................................................................................................33

7.2.

HYSICAL

AYER

UNCTIONAL

VERVIEW

...............................................................................................................33

7.2.1.

Auto-Negotiation for UTP ....................................................................................................................................33

7.2.2.

10Base-T Transmit Function ................................................................................................................................33

7.2.3.

10Base-T Receive Function ..................................................................................................................................33

7.2.4.

Link Monitor.........................................................................................................................................................33

7.2.5.

100Base-TX Transmit Function............................................................................................................................33

7.2.6.

100Base-TX Receive Function..............................................................................................................................34

7.2.7.

Power-Down Mode...............................................................................................................................................34

7.2.8.

Crossover Detection and Auto Correction ...........................................................................................................34

7.2.9.

Polarity Detection and Correction .......................................................................................................................34

7.3.

ENERAL

UNCTION

VERVIEW

................................................................................................................................35

7.3.1.

Power-on Sequence ..............................................................................................................................................35

RTL8306E

Datasheet

Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller

with Dual MII/RMII Interfaces

iv Track ID: JATR-2265-11 Rev. 1.1

7.3.2. Reset .....................................................................................................................................................................36

7.3.3. Setup and Configuration.......................................................................................................................................37

7.3.4. Serial EEPROM Example: 24LC01/02/04 ...........................................................................................................38

7.3.4.1 24LC02/04 Device Operation .......................................................................................................................................38

7.3.4.2 EEPROM Size Selection...............................................................................................................................................40

7.3.5. SMI .......................................................................................................................................................................40

7.3.6. Head-Of-Line Blocking ........................................................................................................................................41

7.3.7. Filtering/Forwarding Reserved Control Frame...................................................................................................41

7.3.8. Loop Detection .....................................................................................................................................................41

7.3.9. MAC Local Loopback Return to External ............................................................................................................44

7.3.10. Reg.0.14 PHY Digital Loopback Return to Internal........................................................................................45

7.3.11. 1.8V Power Generation ...................................................................................................................................46

7.3.12. Crystal/Oscillator ............................................................................................................................................46

8. ADVANCED FUNCTION DESCRIPTION...................................................................................................................47

8.1. ACL FUNCTION .........................................................................................................................................................47

8.2. MAC LIMIT ...............................................................................................................................................................48

8.3. PORT ISOLATION ........................................................................................................................................................48

8.4. VLAN FUNCTION ......................................................................................................................................................48

8.4.1. Description ...........................................................................................................................................................48

8.4.2. Port-Based VLAN .................................................................................................................................................50

8.4.3. IEEE 802.1Q Tagged-VID Based VLAN ..............................................................................................................52

8.4.4. Insert/Remove/Replace Tag..................................................................................................................................53

8.4.5. VLAN Translation.................................................................................................................................................53

8.4.6. QinQ Function......................................................................................................................................................53

8.4.7. Ingress and Egress Rules......................................................................................................................................53

8.5. IEEE 802.1P REMARKING FUNCTION.........................................................................................................................54

8.6. QOS FUNCTION ..........................................................................................................................................................55

8.6.1. Bandwidth Control ...............................................................................................................................................55

8.6.1.1 Introduction...................................................................................................................................................................55

8.6.1.2 Input (RX) Bandwidth Control .....................................................................................................................................56

8.6.2. Priority Assignment..............................................................................................................................................56

8.6.2.1 Queue Number Selection ..............................................................................................................................................57

8.6.2.2 Port-Based Priority Assignment....................................................................................................................................57

8.6.2.3 IEEE 802.1p/Q-Based Priority Assignment..................................................................................................................57

8.6.2.4 DSCP-Based Priority Assignment ................................................................................................................................57

8.6.2.5 12-Bit VLAN ID Priority..............................................................................................................................................57

8.6.2.6 IP Address-Based Priority.............................................................................................................................................57

8.6.2.7 IGMP/MLD-Based Priority ..........................................................................................................................................58

8.6.2.8 CPU Tag-Based Priority ...............................................................................................................................................58

8.6.2.9 ACL-Based Priority Assignment ..................................................................................................................................58

8.6.2.10 Packet Priority Selection...............................................................................................................................................58

8.6.2.11 Priority Controlled By Strapping Pin............................................................................................................................59

8.7. LOOKUP TABLE FUNCTION ........................................................................................................................................60

8.7.1. Function Description............................................................................................................................................60

8.7.2. Address Search, Learning, and Aging ..................................................................................................................60

8.7.3. Lookup and CAM Table Definition ......................................................................................................................62

8.7.3.1 Lookup Table Access....................................................................................................................................................62

8.7.3.2 Least Recently Used (LRU) Function Description .......................................................................................................62

8.8. MIBS FUNCTION........................................................................................................................................................63

8.8.1. MIB Counter Description.....................................................................................................................................63

8.8.2. MIB Counter Enable/Clear ..................................................................................................................................63

8.8.3. MIB Counter Timeout...........................................................................................................................................64

8.9. STORM FILTER FUNCTION ..........................................................................................................................................64

8.9.1. Definition..............................................................................................................................................................64

8.9.2. Type 1 Storm Filter...............................................................................................................................................64

RTL8306E

Datasheet

Single-Chip 6-Port 10/100Mbps Ethernet Switch Controller

with Dual MII/RMII Interfaces

v Track ID: JATR-2265-11 Rev. 1.1

8.9.3. Type 2 Storm Filter...............................................................................................................................................65

8.10. CPU INTERRUPT FUNCTION .......................................................................................................................................66

8.11. IGMP & MLD SNOOPING FUNCTION.........................................................................................................................67

8.12. CPU TAG FUNCTION..................................................................................................................................................68

8.13. IEEE 802.1X FUNCTION.............................................................................................................................................70

8.13.1. Port-Based Access Control..............................................................................................................................70

8.13.2. MAC-Based Access Control.............................................................................................................................70

8.14. IEEE 802.1D FUNCTION ............................................................................................................................................71

8.15. INPUT & OUTPUT DROP FUNCTION ............................................................................................................................73

8.16. PORT MIRRORING ......................................................................................................................................................74

8.17. LED FUNCTION..........................................................................................................................................................75

8.17.1. RTL8306E Controlling LED............................................................................................................................77

8.17.2. CPU Controlling LED .....................................................................................................................................77

8.18. GREEN ETHERNET......................................................................................................................................................78

8.19. ENERGY-EFFICIENT ETHERNET (EEE) .......................................................................................................................78

8.20. WAKE-ON-LAN (WOL) ............................................................................................................................................79

8.21. CPU PORT TRAFFIC RATE MONITOR .........................................................................................................................79

8.22. CABLE DIAGNOSIS .....................................................................................................................................................79

9. REGISTER DESCRIPTIONS.........................................................................................................................................80

9.1. REGISTER LIST ...........................................................................................................................................................80

9.2. PHY 0 REGISTERS......................................................................................................................................................82

9.2.1. PHY 0 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................82

9.2.2. PHY 0 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................83

9.2.3. PHY 0 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................83

9.2.4. PHY 0 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................84

9.2.5. PHY 0 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................84

9.2.6. PHY 0 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................85

9.2.7. PHY 0 Register 16 (Page 0, 1, 2, 3): Global Control 0........................................................................................86

9.2.8. PHY 0 Register 18 (Page 0, 1): Global Control 2................................................................................................87

9.2.9. PHY 0 Register 19 (Page 0, 1): Global Control 3................................................................................................87

9.2.10. PHY 0 Register 22 (Page 0, 1): Port 0 Control Register 0..............................................................................88

9.2.11. PHY 0 Register 24 (Page 0, 1): Port 0 Control Register 1..............................................................................89

9.3. PHY 1 REGISTERS......................................................................................................................................................89

9.3.1. PHY 1 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................89

9.3.2. PHY 1 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................89

9.3.3. PHY 1 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................89

9.3.4. PHY 1 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................89

9.3.5. PHY 1 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................89

9.3.6. PHY 1 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................90

9.3.7. PHY 1 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................90

9.3.8. PHY 1 Register 24 (Page 0, 1): Port 1 Control Register 1...................................................................................90

9.4. PHY 2 REGISTERS......................................................................................................................................................91

9.4.1. PHY 2 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................91

9.4.2. PHY 2 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................91

9.4.3. PHY 2 Register 2 (Page 0, 1, 2, 3): PHY Identifier 1 ...........................................................................................91

9.4.4. PHY 2 Register 3 (Page 0, 1, 2, 3): PHY Identifier 2 ...........................................................................................91

9.4.5. PHY 2 Register 4 (Page 0, 1, 2, 3): Auto-Negotiation Advertisement..................................................................91

9.4.6. PHY 2 Register 5 (Page 0, 1, 2, 3): Auto-Negotiation Link Partner Ability.........................................................91

9.4.7. PHY 2 Register 22 (Page 0, 1): Port 1 Control Register 0...................................................................................91

9.4.8. PHY 2 Register 23 (Page 0, 1): Global Option Register 1...................................................................................91

9.4.9. PHY 2 Register 24 (Page 0, 1): Port 2 Control Register 2...................................................................................92

9.5. PHY 3 REGISTERS......................................................................................................................................................92

9.5.1. PHY 3 Register 0 (Page 0, 1, 2, 3): Control.........................................................................................................92

9.5.2. PHY 3 Register 1 (Page 0, 1, 2, 3): Status ...........................................................................................................92

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