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NVP6158C数据手册/驱动程序
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REVISION HISTORY
NVP6158C Data sheet
Rev.
Date.
Description
Note
REV 0.0
2017-08-22
Initial Draft
-
© Copyright Nextchip Corporations, Ltd., 2017
All Rights Reserved.
Printed in Korea 2017
Nextchip and the Nextchip Logo are trademarks of Nextchip Corporation in Korea and/or other countries.
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for
use in implantation or other life support application where malfunction may result in injury or death to persons. The information contained in
this document does not affect or change Nextchip's product specification or warranties. Nothing in this document shall operate as an express
or implied license or indemnity under the intellectual property rights of Nextchip or third parties. All information contained in this document was
obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will Nextchip be liable for
damages arising directly or indirectly from any use of the information contained in this document.
Nextchip Corporation Ltd
8F, Twosun Venture Forum Bldg., 323, Pangyo-ro, Bundang-gu, Seongnam-si, Gyeonggi-do, Korea 463-400
Nextchip's home page can be found at:
http://www.nextchip.com
2017.08.22 (REV 0.0) NVP6158C Data sheet
www.nextchip.com
3/87
Product Overview
NVP6158C includes Universal 4-Channel RX and 5-Channel Audio Codec. It delivers high quality ALL analog HD with NTSC/PAL image. It
accepts separate CVBS, COMET, Universal 1M ~ 8M@7.5P inputs from Camera and the other video signal sources. It digitizes and decodes
Analog video signal into digital video components which represents 8-bit BT.656/BT.1120 4:2:2 byte interleave format with 74.25,148.5 and
297MHz multiplexed.
NVP6158C includes Clock PLL, so each output byte interleave function available. Especially, It is able to use same transmission cable with
conventional one for COMET(SD level), 1M(HD level), 2M(FHD level) , 4M(QHD level), 8M 7.5P(UHD level), and they provide the superior-
image quality by minimizing the interference when separating Y and C.
5-Channel Audio Codec is 4-Channel Voice/1-Channel Mic PCM Codec which handles voice band signals(300Hz~3400Hz) with 8bit/16bit
linear PCM, 8bit G.711(u-law, a-law) PCM. Built-in audio controller can generate digital outputs for recording/mixing and accepts digital input
for playback.
4-Channel Universal Coaxial Communication Protocol communicates between controller(DVR) and camera on the video signal through
coaxial cable.
Features
1. Video Decoder
Input Formats
- 4CH Video Input
: CVBS / COMET
: Universal 1M~2M@ 25/30P, 3M@18P, 4M 15P, 5M@12.5P,
8M 7.5P
Output Formats
- Output in BT.656/BT.1120 4:2:2 , 1 port 1Mux or 2Mux byte
interleave format
- Support Sync Separate BT.601 Format (CLK/ H,V-SYNC/
8’bit DATA)
Image Signal Processor
-. Support Video Standard Auto-Detection for Each CH
-. Support 2*Video Output Port, Each Port Video Output Format
Selectable
-. On Chip Analog CLAMP/Anti-aliasing Filter and EQ Filter
-. Robust Sync detection for weak and unstable signals
-. High-performance adaptive comb filter and Notch Filter
-. Programmable H/V Peaking filter for Luminance
-. CTI (Chrominance Transient Improvement)
-. Color compensation for PAL
-. IF compensation filter
-. Robust No-video detection
-. Programmable Brightness, Contrast, Saturation and Hue
-. Programmable Picture Quality Control
-. Programmable Gamma Correction
2. Audio Codec
- 4-Ch Voice / 1-Ch Mic Record, 1-Ch Playback
- 10bit pipe-line ADC / 1*DAC
- In/output Analog PGA Control
- Linear PCM (8bit/16bit, 8K/16K/32K)
- G.711 a-law/u-law (8bits, 8K/16K/32K)
- Input Mixing, Digital Volume, Mute Detection
- SSP/DSP/I2S Interface (Master/Slave mode)
- Cascade mode (up to 4 cascade support)
: 18-Channel recording (with 2 channel mic recording), mixing
output, playback
3. MISC
- Built in Clock PLL
- Single 27M Oscillator for all video standards
- Built in 4-Ch Motion Detector(32x24)
- Support Coaxial Protocols for All Video Standard
- Support Each Channel MPP Pin and IRQ Pin
- Support I2C serial Interface
4. Operating Voltage
- 3.3V/1.2V Supply Voltage
5. Ordering information
DEVICE
PACKAGE
TEMPERATURE RANGE
NVP6158C
88eQFN
0 ~ 70 ℃
6. Related Products
- HI3520D-V300 / HI3521A / HI3531A
2017.08.22 (REV 0.0) NVP6158C Data sheet
www.nextchip.com
4/87
Functional block diagram
YC
Seperator
Y
Processor
Clamp/EQ
Control
Analog
Clamp
EQ
Anti-
Aliasing
Filter
ADC
AGC
WPD
HPLL
Gamma
C
Processor
Output
Formatter
ACC
FSC Lock
Motion
Detector
Coaxial
Communicator
PLL
I2C
Interface
Time
Multiplexer
AFE
DAC
Decimation
Filter
Interpolation
Filter
Compressor
Expander
+
Volume
Control
Mute
Detector
Cascade
TX
Cascade
RX
NR
Filter
Volume
Control
Video Decoder 4Ch
Video Decoder 4Ch
Audio Decoder 5Ch/Encoder 1Ch
Audio Decoder 5Ch/Encoder 1Ch
MPP1~4
MPP1~4
SCL/SDA
SCL/SDA
AIN1~4
MICIN
AIN1~4
MICIN
AOUT
AOUT
VIN1~4
VIN1~4
VDO1~2[7:0]
VDO1~2[7:0]
ACLK_REC
ACLK_REC
ASYNC_REC
ASYNC_REC
ADATA_REC
ADATA_REC
ADATA_CASO
ADATA_CASO
ACLK_PB
ACLK_PB
ASYNC_PB
ASYNC_PB
ADATA_PB
ADATA_PB
ADATA_CASI
ADATA_CASI
2017.08.22 (REV 0.0) NVP6158C Data sheet
www.nextchip.com
5/87
TABLE OF CONTENTS
Revision History ......................................................................................................................................................... 2
Contents of Tables ...................................................................................................................................................... 7
Contents of Figures .................................................................................................................................................... 8
Chapter 1 PIN INFORMATION ................................................................................................................................ 9
1.1 PIN ASSIGNMENTS ................................................................................................................................... 9
1.2 PIN DESCRIPTION .................................................................................................................................. 10
Chapter 2 UNIVERSAL RX(1M to 8M7.5P) .......................................................................................................... 12
2.1 FUNCTIONAL OVERVIEW ...................................................................................................................... 12
2.1 ANALOG FRONT END (CLAMP, ANTI-ALIASING FILTER, EQ FILTER) ................................................ 13
2.2 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION) ................................... 13
2.3 YCS (Y/C SEPARATOR) .......................................................................................................................... 13
2.4 LUMA PROCESSING ............................................................................................................................... 13
2.5 CHROMA PROCESSING ......................................................................................................................... 13
2.6 DATA OUTPUT ORDER & DIRECTION CONTROL ................................................................................ 14
2.7 OUTPUT FORMAT ................................................................................................................................... 15
2.7.1 ITU-R BT.656/BT.1120 FORMAT ................................................................................................... 15
2.7.2 ITU-R BT.601 FORMAT ................................................................................................................. 15
2.7.3 VIDEO OUTPUT TIMING INFORMATION .................................................................................... 16
2.8 OUTPUT MODE ....................................................................................................................................... 18
2.8.1 SINGLE OUTPUT MODE .............................................................................................................. 18
2.8.2 2-MULTIPLEX OUTPUT MODE .................................................................................................... 19
2.8.3 4-MULTIPLEX OUTPUT MODE .................................................................................................... 20
2.9 297MHz INTERFACE AND MULTI STANDARD OUTPUT MODE ........................................................... 22
2.10 Video Frame Control ................................................................................................................................. 22
2.11 MOTION DETECTOR ............................................................................................................................... 23
Chapter 3 AUDIO CODEC ..................................................................................................................................... 24
3.1 Record Output .......................................................................................................................................... 24
3.1.1 Data Output Interface .................................................................................................................... 25
3.1.2 2/4/8/16-Channel Data Output(256 fs) .......................................................................................... 26
3.1.3 2/4/8/16-Channel Audio Data Output with 2-Channel Mic Data(320 fs) ........................................ 27
3.1.4 ADATA_SP Output ......................................................................................................................... 28
3.2 Playback Output ....................................................................................................................................... 29
3.3 Audio Detection ........................................................................................................................................ 29
3.4 Cascade Operation ................................................................................................................................... 29
Chapter 4 COAXIAL PROTOCOL ......................................................................................................................... 30
4.1 PELCO PROTOCOL ................................................................................................................................ 30
4.2 A-CP(AHD-Coaxial protocol) .................................................................................................................... 31
Chapter 5 I2C INTERFACE ................................................................................................................................... 33
Chapter 6 REGISTER DESCRIPTION .................................................................................................................. 34
6.1 REGISTER ADDRESS ............................................................................................................................. 34
6.1.1 BANK0 Register(0x00~0x1F) : VIDEO .......................................................................................... 34
6.1.2 BANK0 Register(0x20~0x3F) : VIDEO .......................................................................................... 35
6.1.3 BANK0 Register(0x40~0x5F) : VIDEO .......................................................................................... 36
6.1.4 BANK0 Register(0x60~0x7F) : VIDEO .......................................................................................... 37
6.1.5 BANK0 Register(0x80~0xA3) : VIDEO_ENABLE & Delay ............................................................ 38
6.1.6 BANK0 Register(0xA8~0xF5) : STATUS ....................................................................................... 39
6.1.7 BANK1 Register(0x00~0x1F) : AUDIO .......................................................................................... 40
6.1.8 BANK1 Register(0x20~0x44) : AUDIO .......................................................................................... 41
6.1.9 BANK1 Register(0x80~0x9F) : IP Power Down ............................................................................ 42
6.1.10 BANK1 Register(0xB0~0xBF) : MPP ............................................................................................. 42
6.1.11 BANK1 Register(0xC0~0xCF) : OUTPUT PORT .......................................................................... 42
6.1.12 BANK2 Register(0x00~0x1F) : MOTION ....................................................................................... 43
6.1.13 BANK3~4 Register(0x00~0x7F / 0x80~0xFF ) : COAXIAL ........................................................... 44
6.1.14 BANK3~4 Register(0x00~0x1F / 0x80~0x9F ) : COAXIAL CH1~4 ............................................... 45
6.1.15 BANK3~4 Register(0x20~0x5F / 0xA0~0xDF ) : COAXIAL CH1~4 .............................................. 46
6.1.16 BANK3~4 Register(0x60~0x79 / 0xE0~0xF9 ) : COAXIAL CH1~4 ............................................... 47
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