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MT53E256M32D2DS-053.pdf
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MT53E256M32D2DS -镁光LPDDR4 datasheet
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LPDDR4/LPDDR4X SDRAM
MT53E256M16D1, MT53E256M32D2
Features
This data sheet is for LPDDR4 and LPDDR4X unified
product based on LPDDR4X information. Refer to
LPDDR4 setting section LPDDR4 1.10V V
DDQ
at the
end of this data sheet.
• Ultra-low-voltage core and I/O power supplies
– V
DD1
= 1.70–1.95V; 1.80V nominal
– V
DD2
= 1.06–1.17V; 1.10V nominal
– V
DDQ
= 1.06–1.17V; 1.10V nominal
or Low V
DDQ
= 0.57–0.65V; 0.60V nominal
• Frequency range
– 2133–10 MHz (data rate range: 4266–20 Mb/s/
pin)
• 16n prefetch DDR architecture
• 8 internal banks per channel for concurrent opera-
tion
• Single-data-rate CMD/ADR entry
• Bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies (RL/WL)
• Programmable and on-the-fly burst lengths (BL =
16, 32)
• Directed per-bank refresh for concurrent bank op-
eration and ease of command scheduling
• Up to 8.5 GB/s per die
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Selectable output drive strength (DS)
• Clock-stop capability
• RoHS-compliant, “green” packaging
• Programmable V
SS
(ODT) termination
Options Marking
• V
DD1
/V
DD2
/V
DDQ
: 1.80V/1.10V/1.10V or
0.60V
E
• Array configuration
– 256 Meg × 16 (1 channel ×16 I/O) 256M16
– 256 Meg × 32 (2 channels ×16 I/O) 256M32
• Device configuration
– 256M16 × 1 die in package D1
– 256M16 × 2 die in package D2
• FBGA “green” package
– 200-ball WFBGA (10mm × 14.5mm ×
0.8mm, Ø0.35 SMD)
DS
• Speed grade, cycle time
– 535ps @ RL = 32/36 -053
– 468ps @ RL = 36/40 -046
• Operating temperature range
– –30°C to +85°C WT
• Revision :B
Table 1: Key Timing Parameters
Speed
Grade
Clock Rate
(MHz)
Data Rate
(Mb/s/pin)
WRITE Latency READ Latency
Set A Set B DBI Disabled DBI Enabled
-053 1866 3733 16 30 32 36
-046 2133 4266 18 34 36 40
Micron Confidential and Proprietary
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
Features
CCM005-554574167-10527
200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. F 6/19 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
SDRAM Addressing
The table below shows 4Gb single-channel die configuration used in the package.
Table 2: Device Configuration
256M16 (4Gb/Package) 256M32 (8Gb/Package)
Die configuration Channel A, rank 0 ×16 mode × 1 die ×16 mode × 1 die
Channel B, rank 0 – ×16 mode × 1 die
Die addressing Bank address BA[2:0] BA[2:0]
Row addresses R[14:0] R[14:0]
Column addresses C[9:0] C[9:0]
Note:
1. Refer to Package Block Diagrams section and Monolithic Device Addressing section.
Micron Confidential and Proprietary
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
Features
CCM005-554574167-10527
200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. F 6/19 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
Part Number and Part Marking Information
Part Number Ordering
Micron LPDDR4 devices are available in different configurations and densities. Verify valid part numbers by using
Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit
www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Chart
MT 53 E 256M32 D2 DS -053 WT :B
Micron Technology
Product Family
53 = Mobile LPDDR4 SDRAM
Operating Voltage
E = 1.10V V
DD2
/0.60V or 1.10V V
DDQ
Configuration
128M16 = 128 Meg x 16
128M32 = 128 Meg x 32
256M16 = 256 Meg x 16
256M32 = 256 Meg x 32
384M32 = 384 Meg x 32
512M32 = 512 Meg x 32
768M32 = 768 Meg x 32
1024M32 = 1024 Meg x 32
Addressing
D1 = LPDDR4, 1 die
D2 = LPDDR4, 2 die
D4 = LPDDR4, 4 die
Design Revision
:A, :B, :C, :D, :E
Operating Temperature
WT = –30°C to +85°C
Automotive Certification (option)
A = Package-level burn-in
Blank = Standard
Cycle Time
-062 = 625ps,
t
CK RL = 28/32
-053 = 535ps,
t
CK RL = 32/36
-046 = 468ps,
t
CK RL = 36/40
Package Codes
DS = 200-ball WFBGA 10 x 14.5 x 0.8mm (Ø0.35 SMD)
DT = 200-ball VFBGA 10 x 14.5 x 0.95mm (Ø0.35 SMD)
NP = 200-ball WFBGA 10 x 14.5 x 0.8mm (Ø0.28 SMD)
NQ = 200-ball VFBGA 10 x 14.5 x 0.95mm (Ø0.28 SMD)
GZ = 200-ball WFBGA 11 x 14.5 x 0.8mm (Ø0.28 SMD)
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Micron Confidential and Proprietary
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
Features
CCM005-554574167-10527
200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. F 6/19 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
Contents
Important Notes and Warnings ....................................................................................................................... 17
General Description ....................................................................................................................................... 18
General Notes ............................................................................................................................................ 18
Package Block Diagrams ................................................................................................................................. 19
Ball Assignments and Descriptions ................................................................................................................. 20
Package Dimensions ....................................................................................................................................... 23
MR0, MR[6:5], MR8, MR13, MR24 Definition ................................................................................................... 24
LPDDR4 I
DD
Parameters ................................................................................................................................. 25
LPDDR4X I
DD
Parameters ............................................................................................................................... 27
Functional Description ................................................................................................................................... 29
Monolithic Device Addressing ......................................................................................................................... 30
Simplified Bus Interface State Diagram ............................................................................................................ 33
Power-Up and Initialization ............................................................................................................................ 34
Voltage Ramp ............................................................................................................................................. 35
Reset Initialization with Stable Power .......................................................................................................... 37
Power-Off Sequence ....................................................................................................................................... 38
Controlled Power-Off .................................................................................................................................. 38
Uncontrolled Power-Off .............................................................................................................................. 38
Mode Registers ............................................................................................................................................... 39
Mode Register Assignments and Definitions ................................................................................................ 39
Commands and Timing .................................................................................................................................. 65
Truth Tables ................................................................................................................................................... 65
ACTIVATE Command ..................................................................................................................................... 67
Read and Write Access Modes ......................................................................................................................... 69
Preamble and Postamble ................................................................................................................................ 69
Burst READ Operation .................................................................................................................................... 73
Read Timing ............................................................................................................................................... 75
t
LZ(DQS),
t
LZ(DQ),
t
HZ(DQS),
t
HZ(DQ) Calculation ..................................................................................... 75
t
LZ(DQS) and
t
HZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 76
t
LZ(DQ) and
t
HZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 77
Burst WRITE Operation .................................................................................................................................. 79
Write Timing .............................................................................................................................................. 82
t
WPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 83
t
WPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 83
MASK WRITE Operation ................................................................................................................................. 84
Mask Write Timing Constraints for BL16 ...................................................................................................... 86
Data Mask and Data Bus Inversion (DBI [DC]) Function ................................................................................... 88
WRITE and MASKED WRITE Operation DQS Control (WDQS Control) ............................................................. 92
WDQS Control Mode 1 – Read-Based Control .............................................................................................. 92
WDQS Control Mode 2 – WDQS_On/Off ...................................................................................................... 92
Preamble and Postamble Behavior .................................................................................................................. 96
Preamble, Postamble Behavior in READ-to-READ Operations ...................................................................... 96
READ-to-READ Operations – Seamless ........................................................................................................ 97
READ-to-READ Operations – Consecutive ................................................................................................... 98
WRITE-to-WRITE Operations – Seamless ................................................................................................... 105
WRITE-to-WRITE Operations – Consecutive ............................................................................................... 108
PRECHARGE Operation ................................................................................................................................. 112
Burst READ Operation Followed by Precharge ............................................................................................ 112
Burst WRITE Followed by Precharge ........................................................................................................... 113
Auto Precharge .............................................................................................................................................. 114
Micron Confidential and Proprietary
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
Features
CCM005-554574167-10527
200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. F 6/19 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
Burst READ With Auto Precharge ............................................................................................................... 114
Burst WRITE With Auto Precharge .............................................................................................................. 115
RAS Lock Function .................................................................................................................................... 119
Delay Time From WRITE-to-READ with Auto Precharge .............................................................................. 120
REFRESH Command ..................................................................................................................................... 121
Burst READ Operation Followed by Per Bank Refresh .................................................................................. 127
Refresh Requirement ..................................................................................................................................... 128
SELF REFRESH Operation .............................................................................................................................. 129
Self Refresh Entry and Exit ......................................................................................................................... 129
Power-Down Entry and Exit During Self Refresh ......................................................................................... 130
Command Input Timing After Power-Down Exit ......................................................................................... 131
Self Refresh Abort ...................................................................................................................................... 132
MRR, MRW, MPC Commands During
t
XSR,
t
RFC ........................................................................................ 132
Power-Down Mode ........................................................................................................................................ 135
Power-Down Entry and Exit ....................................................................................................................... 135
Input Clock Stop and Frequency Change ........................................................................................................ 145
Clock Frequency Change – CKE LOW ......................................................................................................... 145
Clock Stop – CKE LOW ............................................................................................................................... 145
Clock Frequency Change – CKE HIGH ........................................................................................................ 145
Clock Stop – CKE HIGH ............................................................................................................................. 146
MODE REGISTER READ Operation ................................................................................................................ 147
MRR After a READ and WRITE Command .................................................................................................. 148
MRR After Power-Down Exit ...................................................................................................................... 150
MODE REGISTER WRITE ............................................................................................................................... 151
Mode Register Write States ......................................................................................................................... 152
V
REF
Current Generator (VRCG) ..................................................................................................................... 153
V
REF
Training ................................................................................................................................................. 155
V
REF(CA)
Training ........................................................................................................................................ 155
V
REF(DQ)
Training ....................................................................................................................................... 160
Command Bus Training ................................................................................................................................. 165
Command Bus Training Mode .................................................................................................................... 165
Training Sequence for Single-Rank Systems ................................................................................................ 166
Training Sequence for Multiple-Rank Systems ............................................................................................ 167
Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 168
Write Leveling ............................................................................................................................................... 172
Mode Register Write-WR Leveling Mode ..................................................................................................... 172
Write Leveling Procedure ........................................................................................................................... 172
Input Clock Frequency Stop and Change .................................................................................................... 173
MULTIPURPOSE Operation ........................................................................................................................... 176
Read DQ Calibration Training ........................................................................................................................ 181
Read DQ Calibration Training Procedure .................................................................................................... 181
Read DQ Calibration Training Example ...................................................................................................... 183
MPC[READ DQ CALIBRATION] After Power-Down Exit ............................................................................... 184
Write Training ............................................................................................................................................... 184
Internal Interval Timer .............................................................................................................................. 190
DQS Interval Oscillator Matching Error ...................................................................................................... 192
OSC Count Readout Time .......................................................................................................................... 193
Thermal Offset .............................................................................................................................................. 195
Temperature Sensor ...................................................................................................................................... 195
ZQ Calibration ............................................................................................................................................... 196
ZQCAL Reset ............................................................................................................................................. 197
Multichannel Considerations ..................................................................................................................... 198
Micron Confidential and Proprietary
200b: x16/x32 LPDDR4/LPDDR4X SDRAM
Features
CCM005-554574167-10527
200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. F 6/19 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2017 Micron Technology, Inc. All rights reserved.
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