DEI1016芯片：航空航天A429总线接口详解

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"DEI1016是一款专用于航空航天领域的芯片，主要支持A429总线协议。这款芯片设计有双接收器和一个发射器，适用于标准的串行数字数据总线与16位宽的数字数据总线之间的接口转换。" DEI1016芯片是Device Engineering Inc.生产的一款高性能接口芯片，其主要特点是能够适应多种ARINC协议，包括429、571、575和706等。这使得它在航空电子系统中具有广泛的应用潜力，尤其是在需要处理不同协议数据传输的场合。该芯片的核心特性包括： 1. 双接收器和一个发射器：DEI1016具备两个独立工作的接收通道，可以同时接收来自两个不同数据源的信息，而发射器则包含一个8字节乘以32位的缓冲区，用于存储待发送的数据块。 2. 自我环绕测试模式：内置的自检功能允许芯片在不中断正常工作的情况下进行内部功能测试，确保系统的稳定性和可靠性。 3. 可配置的字长：用户可以根据需求将操作字长设置为25位或32位，以适应不同的数据传输要求。 4. 奇偶校验状态：支持生成和检测接收及发送字的奇偶校验，增强数据传输的准确性。 5. 8字节发射器缓冲区：提供足够的存储空间，允许主机一次性写入大量数据，并按需分批传输。 6. 低功耗CMOS工艺：采用低功耗技术，降低了运行时的能耗，适合于对电源要求严格的航空应用环境。 7. 温度范围：DEI1016有两种版本，分别支持扩展温度范围（-55℃至+85℃）和军用温度范围（-55℃至+125℃），确保在极端环境下也能正常工作。 8. 主机可编程控制寄存器：通过这个寄存器，用户可以设置各种操作选项，以定制芯片的行为以满足特定系统需求。 DEI1016芯片是一个强大的接口解决方案，专为航空航天领域设计，能够处理复杂的通信协议并提供高可靠性数据传输。它的灵活性、可配置性以及对多种ARINC协议的支持，使其成为航空电子系统设计中的理想选择。

01/07/2005

Table 6: DEI1016 Control Word

AME DATA BIT DESCRIPTION

PAREN D4

Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always

inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and

Logic “1” on PAREN inserts parity on bit 32.

/SLFTST

Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter

outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going

into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is

active during test mode.

SDEN1

S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.

X1, Y1

D7, D8

S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then incoming

receiver data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver

1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data

bit 10.

SDEN2

S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1.

X2, Y2

D10, D11

S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then incoming

receiver data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver

2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial

data bit 10.

PARCK D12

Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0”

selects normal odd parity; logic “1” selects even parity.

TXSEL

D13

Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the

clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate

divided by 80.

RCVSEL

D14

Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data

rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO

data rate is the input clock divided by 80.

WLSEL

D15

Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic ”1” sets

them to a 25 bit word format.

NOT USED D0-D3

When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will no

be used on the chip.

NOTES

1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.

2) SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a

master reset has been removed.

3) TXSEL should only be changed during the time that TXR is high or Master Reset is low.

4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and

Receiver 2 should be ignored.

5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or

transmitted following the control word write operation.

Functional Description:

The DEI 1016 supports a number of various options

which are selected by data written into the control

16-bit data bus when the /LDCW signal is pulsed to a

logic “0”. The twelve control bits control the following

functions:

1) Word Length (32 or 25 bits)

2) Transmitter bit 32 (Parity or Data)

3) Wrap around self test.

4) Source Destination code checking of received data.

5) Transmitter parity (even or odd)

6) Transmitter and Receiver data rate (100 or 12.5 kbps)

Table 5: Control Register Format

BIT SYMBOL BIT SYMBOL

D15 (MSB) WLSEL D7 X1

D14 RCVSEL D6 SDENB1

D13 TXSEL D5 /SLFTST

D12 PARCK D4 PAREN

D11 Y2 D3

OT USED

D10 X2 D2

OT USED

D9 SDENB2 D1

OT USED

D8 Y1 D0

OT USED

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