systemverilog for verification 绿皮书第三版（最新）课后习题答案.pdf

©Greg Tumbush, ©Chris Spear 2011 Page 1 of 63 Solutions Manual v1.2

This manual contains solutions to Exercises at the end of each chapter.

Table of Contents

1 Solution to Exercises for Chap 1 Verification Guidelines ...................................................................... 2

2 Solution to Exercises for Chap 2 Data Types ......................................................................................... 4

3 Solution to Exercises for Chap 3 Procedural Statements and Routines ............................................. 12

4 Solution to Exercises for Chap 4 Connecting the Testbench and Design ........................................... 16

5 Solution to Exercises for Chap 5 Basic OOP ........................................................................................ 20

12 Solution to Exercises for Chap 12 Interfacing with C ...................................................................... 66

©Greg Tumbush, ©Chris Spear 2011 Page 2 of 63 Solutions Manual v1.2

1 Solution to Exercises for Chap 1 Verification Guidelines

1. Write a verification plan for an Arithmetic Logic Unit (ALU) with:

 Asynchronous active high input reset

 Input clock

 4-bit signed inputs, A and B

 5-bit signed output C that is registered on the positive edge of input clock.

Solution: There are many solutions to this Exercise. One possible solution is:

Check reset value of output C.

Apply all permutations of max pos, max neg, and 0 to the add and subtract opcodes

Apply 0 and all 1’s to A for bitwise invert input A opcode. Set B to non-all 0 and non-all 1.

Apply 0, all 1’s, and walking 1’s to B for ReductionOR_B opcode. Set A to a value that will yield

the opposite result of B, i.e. if the expected value of B =1, set A to a value so that the bitwise

invert is 0.

Assert reset when output C is 5’b11111.

The first disadvantage to verifying at the block level is testbench complexity if a block has many

interfaces. The testbench can be very complex because all of these interfaces must be modeled.

Another disadvantage is simply that the system is not being tested, just individual blocks. There

is no guarantee that when all the verified blocks are integrated that they will implement the

specification.

3. What are the advantages and disadvantages to testing at the system level? Why?

Solution: The advantage of verifying at the system level is that the final system is being tested

©Greg Tumbush, ©Chris Spear 2011 Page 3 of 63 Solutions Manual v1.2

complex interaction between circuits, and poor control because the testbench has to traverse

many layers of circuitry to manipulate a particular signal.

4. What are the advantages and disadvantages to directed testing? Why?

Solution: The advantages to directed testing are fast testbench development time because no

complex scoreboard or reference model is required, linear progress because each test takes a

similar amount of time to write, and popularity of management because steady progress is being

made.

to better than linear progress, ease of maintenance because if the specification changes only the

scoreboard or reference model needs to change, and a methodology that is reusable and scales

to larger designs.

The disadvantages are that initially no verification is being done due to a more complex

testbench being developed.

©Greg Tumbush, ©Chris Spear 2011 Page 4 of 63 Solutions Manual v1.2

2 Solution to Exercises for Chap 2 Data Types

1. Given the following code sample:

Solution: my_int is 32’h0000_0F00 because the X’s and Z’s in 4-state my_integer resolve

to 0 when assigned to 2-state my_int.

Solution: my_bit is 32768 because my_bit is not signed

Solution: my_short_int1 is -32768 because my_short_int1 is signed

©Greg Tumbush, ©Chris Spear 2011 Page 5 of 63 Solutions Manual v1.2

returns an X but it is resolved to a 0 when assigned to 2-value logic.

Solution: my_logic = 4’hxbecause reading from an out of bounds 4-valued type returns

an X

Solution: my_logicmem= {0,1,2,0} because reading from an out of bounds 2-value type

returns a 0

f) my_logic = my_mem[1];

Solution: my_logic = 4’h5 since my_mem[1] = 8’hA5 but my_logic is only 4-bits wide

g) my_logic = my_logicmem[my_logicmem[4]];

Solution: my_logic =4’h x since my_logicmem[4] returns an X since the index is out of

bounds. my_logicmem[x] = x.

See Chap_2_Data_Types/exercise2 for code.

3. Write the SystemVerilog code to: