UG380 (v2.11) March 22, 2019 www.xilinx.com Spartan-6 FPGA Configuration User Guide
Revision History
The following table shows the revision history for this document.
Date Version Revision
06/24/2009 1.0 Initial Xilinx release.
02/17/2010 2.0
Changed REBOOT command to IPROG command throughout the document.
Chapter 1: In The High-Speed Priority Option, changed the configuration data size to 3.6 Mb (XC6SLX16). In FPGA
Density Migration on page 21, changed the required configuration memory size to 2.6 Mb (XC6SLX9) and 3.6 Mb
(XC6SLX16). In Protecting the FPGA Bitstream against Unauthorized Duplication, clarified which Spartan-6
devices have AES decryption logic.
Chapter 2: Removed the caution statement following Table 2-1. In Figure 2-2, Figure 2-3, Figure 2-6, Figure 2-7,
Figure 2-12, and Figure 2-20, changed VCCO_2 resistor to 2.4 kΩ.; added V
FS
and V
BATT
ports, added the
SUSPEND pin, and added four notes to the end of the Notes section following each figure. In Figure 2-2 and
Figure 2-6, removed “either 2.5V or 3.3V” from note about Spartan-6 FPGA VCCO_2 and the Platform Flash PROM
V
CCO
supply inputs. In Note 12 under Figure 2-12 and Note 10 under Figure 2-20, included PLL lock wait. In
Figure 2-2, changed PROGRAM_B pull-up power to VCCO_2. Removed Slave DIN from Figure 2-4. Added
sentence about SelectMAP unavailability to the first paragraph of SelectMAP Configuration Interface. Added
sentence about toggling to the BUSY description in Table 2-3. In Figure 2-6, added a 4.7 kΩ pull-up to
PROGRAM_B. Added BUSY to Note 14 under Figure 2-6. Added “configuration and” to Note 2 under Figure 2-7.
Moved placement of Table 2-6 and Table 2-7. Removed mention of Winbond’s SPI flash from Table 2-6. Changed
the first paragraph of CSI_B. Revised the RDWR_B section. In Note 1 under Figure 2-9, indicated that CSI_B cannot
be deasserted during the sync word. In Figure 2-12, changed 3.3V to VCCO_2. In Master BPI Configuration
Interface, updated the devices and packages that do not support the BPI interface; indicated A22 and A23 are not
in the CSG225 package; and added “top boot” to parallel NOR flash. In Table 2-7, removed the reference to the
BYTE# port in the HDC and LDC descriptions. In Figure 2-20, connected VCCO_1 and BYTE# to VCCO_1 and
added pull-up resistors to FCS_B, FOE_B, and FWE_B. Added Note 5 and 6 after Figure 2-20. Removed note about
CCLK being free from reflections to avoid double clocking in Board Layout for Configuration Clock (CCLK).
Chapter 4: Changed the last sentence in the first paragraph of ICAP_SPARTAN6. In the first paragraph of
STARTUP_SPARTAN6, changed EOS to configuration.
Chapter 5: Throughout this chapter, included waiting for PLLs to lock along with DCMs. In Table 5-1, added rows
for V
FS
, V
BATT
, and RFUSE; added Note 4; and changed pin name CMP_CS_B to CMPCS_B and updated its
description. Transferred FPGA I/O Pin Settings During Configuration from Chapter 1 and Reserving
Dual-Purpose Configuration Pins (Persist) from Chapter 2. In FPGA I/O Pin Settings During Configuration,
indicated that all user I/Os have optional pull-ups. Added Note 3 to Table 5-2. In Table 5-3, added Note 1 and
revised Note 2. In Table 5-5, changed the values in the “Total Number of Configuration Bits” column. In Device
Power-Up (Step 1), changed the second and third paragraphs and added -4 to the fourth paragraph. In Table 5-11,
added V
FS
and VCCO_5; changed V
FS
and V
BATT
descriptions; deleted “Value” and “Units” columns; added Notes
1, 4, and 5; and updated Note 2 to add V
FS
. Changed the second paragraph following Figure 5-4. Changed the last
paragraph in Check Device ID (Step 5). Added clocking specifics for the sequential state machine in the first
paragraph of Startup (Step 8). In Table 5-17, revised the DCM_LOCK description and moved Note 3 text to Startup
(Step 8). Added new paragraph after Table 5-17. In Loading the Encryption Key, clarified the type of programming
cable and rephrased the last sentence in the last paragraph. Changed the fourth and fifth paragraphs of Loading
Encrypted Bitstreams. Added the eFUSE section. In Table 5-22, changed the values under the “Total Bits” column.
Revised the GENERAL2 and GENERAL4 descriptions in Table 5-30. In Boot History Status Register (BOOTSTS),
changed the description of how this register is reset. In Table 5-48, changed bits 2 and 8 to “Reserved.” In
Figure 5-16, added a buffer between DOUT and DIN. Added sentence prior to Figure 5-16 about the new buffer.
Added the Bitstream Compression section.
Chapter 6: Changed the first paragraph. In Table 6-1, changed the “Configuration Data [15:0]” values for Steps 6
and 12. Changed the step numbers in the first sentence under Table 6-1. Added a sentence on SelectMAP data
ordering to the paragraph preceding Figure 6-2. In Figure 6-2, changed the timing diagram.
Chapter 7: In MultiBoot Overview, changed the last paragraph and removed the caution statement. Made
numerous changes to Fallback Behavior. In Reboot Using ICAP_SPARTAN6, changed “next bitstream” to
“MultiBoot bitstream” in the first paragraph and changed step 2 in the sequence of commands. In Table 7-1,
swapped the values of the Sync words, made changes in the “Explanation” column, and added Note 1 and Note
2. In Watchdog Timer, changed the first sentence in the first three paragraphs.
Chapter 8: On page 142, changed slice to frame in the first bullet, revised the fourth bullet, and removed the bullet
about transceiver DRPs not being masked.
Chapter 9: Changed Table 9-1.
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