DSP28335英文手册.pdf

dsp28335

指导手册

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TMS320x2833x, TMS320x2823x

Technical Reference Manual

Literature Number: SPRUI07

March 2020

SPRUI07–March 2020

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Contents

Preface....................................................................................................................................... 36

1 System Control and Interrupts ............................................................................................. 38

1.1 Flash and OTP Memory Blocks .......................................................................................... 39

1.1.1 Flash Memory...................................................................................................... 39

1.1.2 OTP Memory....................................................................................................... 39

1.1.3 Flash and OTP Power Modes ................................................................................... 39

1.1.4 Flash and OTP Registers ........................................................................................ 44

1.2 Code Security Module (CSM)............................................................................................. 49

1.2.1 Functional Description ............................................................................................ 49

1.2.2 CSM Impact on Other On-Chip Resources .................................................................... 52

1.2.3 Incorporating Code Security in User Applications ............................................................ 53

1.2.4 Do's and Don'ts to Protect Security Logic...................................................................... 58

1.2.5 CSM Features - Summary ....................................................................................... 58

1.3 Clocking and System Control............................................................................................. 59

1.3.1 Clocking ............................................................................................................ 59

1.3.2 OSC and PLL Block............................................................................................... 66

1.3.3 Low-Power Modes Block ......................................................................................... 74

1.3.4 Watchdog Block ................................................................................................... 76

1.3.5 32-Bit CPU Timers 0/1/2 ......................................................................................... 81

1.4 General-Purpose Input/Output (GPIO) .................................................................................. 86

1.4.1 GPIO Module Overview .......................................................................................... 86

1.4.2 Configuration Overview........................................................................................... 92

1.4.3 Digital General Purpose I/O Control ............................................................................ 93

1.4.4 Input Qualification ................................................................................................. 95

1.4.5 GPIO and Peripheral Multiplexing (MUX) ...................................................................... 99

1.4.6 Register Bit Definitions.......................................................................................... 104

1.5 Peripheral Frames ........................................................................................................ 129

1.5.1 Peripheral Frame Registers .................................................................................... 129

1.5.2 EALLOW-Protected Registers ................................................................................. 131

1.5.3 Device Emulation Registers .................................................................................... 135

1.5.4 Write-Followed-by-Read Protection ........................................................................... 137

1.6 Peripheral Interrupt Expansion (PIE)................................................................................... 138

1.6.1 Overview of the PIE Controller................................................................................. 138

1.6.2 Vector Table Mapping........................................................................................... 141

1.6.3 Interrupt Sources................................................................................................. 143

1.6.4 PIE Configuration and Control Registers ..................................................................... 153

1.6.5 External Interrupt Control Registers .......................................................................... 163

2 Boot ROM ........................................................................................................................ 166

2.1 Boot ROM Memory Map ................................................................................................. 167

2.1.1 On-Chip Boot ROM IQmath Tables ........................................................................... 167

2.1.2 CPU Vector Table ............................................................................................... 170

2.2 Bootloader Features...................................................................................................... 171

2.2.1 Bootloader Functional Operation .............................................................................. 171

2.2.2 Bootloader Device Configuration .............................................................................. 173

2.2.3 PLL Multiplier and DIVSEL Selection ......................................................................... 173

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Contents

2.2.4 Watchdog Module ............................................................................................... 174

2.2.5 Taking an ITRAP Interrupt...................................................................................... 174

2.2.6 Internal Pullup Circuit............................................................................................ 174

2.2.7 PIE Configuration ................................................................................................ 174

2.2.8 Reserved Memory ............................................................................................... 174

2.2.9 Bootloader Modes ............................................................................................... 175

2.2.10 Bootloader Data Stream Structure........................................................................... 179

2.2.11 Basic Transfer Procedure ..................................................................................... 183

2.2.12 InitBoot Assembly Routine .................................................................................... 183

2.2.13 SelectBootMode Function .................................................................................... 184

2.2.14 ADC_cal Assembly Routine ................................................................................... 186

2.2.15 CopyData Function ............................................................................................. 187

2.2.16 McBSP_Boot Function ......................................................................................... 188

2.2.17 SCI_Boot Function ............................................................................................. 189

2.2.18 Parallel_Boot Function (GPIO)................................................................................ 191

2.2.19 XINTF_Parallel_Boot Function................................................................................ 197

2.2.20 SPI_Boot Function.............................................................................................. 204

2.2.21 I2C Boot Function .............................................................................................. 207

2.2.22 eCAN Boot Function ........................................................................................... 210

2.2.23 ExitBoot Assembly Routine................................................................................... 212

2.3 Building the Boot Table .................................................................................................. 213

2.3.1 The C2000 Hex Utility........................................................................................... 213

2.3.2 Example: Preparing a COFF File for eCAN Bootloading................................................... 214

2.4 Bootloader Code Overview.............................................................................................. 217

2.4.1 Boot ROM Version and Checksum Information ............................................................. 217

2.4.2 Bootloader Code Revision History............................................................................. 217

3 Enhanced Pulse Width Modulator (ePWM) Module................................................................ 218

3.1 Introduction ................................................................................................................ 219

3.1.1 Submodule Overview............................................................................................ 219

3.1.2 Register Mapping ................................................................................................ 222

3.2 ePWM Submodules ...................................................................................................... 224

3.2.1 Overview .......................................................................................................... 224

3.2.2 Time-Base (TB) Submodule.................................................................................... 228

3.2.3 Counter-Compare (CC) Submodule........................................................................... 236

3.2.4 Action-Qualifier (AQ) Submodule.............................................................................. 242

3.2.5 Dead-Band Generator (DB) Submodule...................................................................... 256

3.2.6 PWM-Chopper (PC) Submodule............................................................................... 261

3.2.7 Trip-Zone (TZ) Submodule ..................................................................................... 265

3.2.8 Event-Trigger (ET) Submodule ................................................................................ 269

3.3 Applications to Power Topologies ...................................................................................... 274

3.3.1 Overview of Multiple Modules ................................................................................. 274

3.3.2 Key Configuration Capabilities ................................................................................. 274

3.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................... 275

3.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................ 279

3.3.5 Controlling Multiple Half H-Bridge (HHB) Converters....................................................... 282

3.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM).......................................... 284

3.3.7 Practical Applications Using Phase Control Between PWM Modules .................................... 288

3.3.8 Controlling a 3-Phase Interleaved DC/DC Converter ....................................................... 289

3.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter....................................... 293

3.4 Registers................................................................................................................... 296

3.4.1 Time-Base Submodule Registers.............................................................................. 296

3.4.2 Counter-Compare Submodule Registers ..................................................................... 300

3.4.3 Action-Qualifier Submodule Registers ........................................................................ 304

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Contents

3.4.4 Dead-Band Submodule Registers ............................................................................. 308

3.4.5 PWM-Chopper Submodule Control Register................................................................. 311

3.4.6 Trip-Zone Submodule Control and Status Registers........................................................ 313

3.4.7 Event-Trigger Submodule Registers .......................................................................... 320

3.4.8 Proper Interrupt Initialization Procedure ...................................................................... 325

4 High-Resolution Pulse Width Modulator (HRPWM)................................................................ 326

4.1 Introduction ................................................................................................................ 327

4.2 Operational Description of HRPWM.................................................................................... 328

4.2.1 Controlling the HRPWM Capabilities.......................................................................... 328

4.2.2 Configuring the HRPWM........................................................................................ 330

4.2.3 Principle of Operation ........................................................................................... 330

4.2.4 Scale Factor Optimizing Software (SFO)..................................................................... 335

4.2.5 HRPWM Examples Using Optimized Assembly Code...................................................... 339

4.3 HRPWM Registers........................................................................................................ 346

4.3.1 Register Summary............................................................................................... 346

4.3.2 Registers and Field Descriptions .............................................................................. 347

5 Enhanced Capture (eCAP) ................................................................................................. 349

5.1 Introduction ................................................................................................................ 350

5.2 Features.................................................................................................................... 350

5.3 Description................................................................................................................. 351

5.4 Capture and APWM Operating Mode .................................................................................. 353

5.5 Capture Mode Description............................................................................................... 355

5.5.1 Event Prescaler .................................................................................................. 356

5.5.2 Edge Polarity Select and Qualifier............................................................................. 356

5.5.3 Continuous/One-Shot Control.................................................................................. 358

5.5.4 32-Bit Counter and Phase Control............................................................................. 359

5.5.5 CAP1-CAP4 Registers .......................................................................................... 359

5.5.6 Interrupt Control.................................................................................................. 359

5.5.7 Shadow Load and Lockout Control............................................................................ 361

5.5.8 APWM Mode Operation......................................................................................... 361

5.6 Application of the eCAP Module ....................................................................................... 364

5.6.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger....................................... 364

5.6.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ........................ 365

5.6.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger..................................... 366

5.6.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ...................... 367

5.7 Application of the APWM Mode......................................................................................... 368

5.7.1 Example 1 - Simple PWM Generation (Independent Channel/s).......................................... 368

5.7.2 Example 2 - Multi-channel PWM Generation With Phase Control ........................................ 368

5.8 eCAP Registers ........................................................................................................... 371

5.8.1 eCAP Base Addresses.......................................................................................... 371

5.8.2 ECAP_REGS Registers......................................................................................... 372

6 Enhanced Quadrature Encoder Pulse (eQEP)....................................................................... 389

6.1 Introduction ................................................................................................................ 390

6.2 Configuring Device Pins ................................................................................................. 392

6.3 Description................................................................................................................. 392

6.3.1 EQEP Inputs...................................................................................................... 392

6.3.2 Functional Description........................................................................................... 393

6.3.3 eQEP Memory Map ............................................................................................. 394

6.4 Quadrature Decoder Unit (QDU) ....................................................................................... 395

6.4.1 Position Counter Input Modes.................................................................................. 395

6.4.2 eQEP Input Polarity Selection.................................................................................. 398

6.4.3 Position-Compare Sync Output ................................................................................ 398

6.5 Position Counter and Control Unit (PCCU)............................................................................ 398

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Contents

6.5.1 Position Counter Operating Modes............................................................................ 398

6.5.2 Position Counter Latch.......................................................................................... 400

6.5.3 Position Counter Initialization .................................................................................. 402

6.5.4 eQEP Position-compare Unit................................................................................... 403

6.6 eQEP Edge Capture Unit ................................................................................................ 404

6.7 eQEP Watchdog .......................................................................................................... 408

6.8 Unit Timer Base........................................................................................................... 409

6.9 eQEP Interrupt Structure ................................................................................................ 410

6.10 eQEP Registers........................................................................................................... 410

6.10.1 eQEP Base Addresses ........................................................................................ 410

6.10.2 EQEP_REGS Registers ....................................................................................... 411

7 Analog-to-Digital Converter (ADC) ...................................................................................... 445

7.1 Features and Implementation ........................................................................................... 446

7.2 ADC Circuit ................................................................................................................ 448

7.2.1 ADC Clocking and Sample Rate Calculations ............................................................... 448

7.2.2 ADC Sample and Hold Circuit and Modeling ................................................................ 450

7.2.3 Reference Selection ............................................................................................. 455

7.2.4 Power-up Sequence and Power Modes ...................................................................... 456

7.2.5 Calibration and Offset Correction.............................................................................. 457

7.3 ADC Interface ............................................................................................................. 461

7.3.1 Input Trigger Description ....................................................................................... 461

7.3.2 Autoconversion Sequencer Principle of Operation .......................................................... 462

7.3.3 ADC Sequencer State Machine................................................................................ 469

7.3.4 Interrupt Operation During Sequenced Conversions ....................................................... 474

7.3.5 ADC to DMA Interface .......................................................................................... 475

7.4 ADC Registers ............................................................................................................ 477

7.4.1 ADCTRL1 Register (Offset = 0h) [reset = 0h]................................................................ 478

7.4.2 ADCTRL2 Register (Offset = 1h) [reset = 0h]................................................................ 480

7.4.3 ADCMAXCONV Register (Offset = 2h) [reset = 0h]......................................................... 483

7.4.4 ADCCHSELSEQ1 Register (Offset = 3h) [reset = 0h] ...................................................... 485

7.4.5 ADCCHSELSEQ2 Register (Offset = 4h) [reset = 0h] ...................................................... 486

7.4.6 ADCCHSELSEQ3 Register (Offset = 5h) [reset = 0h] ...................................................... 487

7.4.7 ADCCHSELSEQ4 Register (Offset = 6h) [reset = 0h] ...................................................... 488

7.4.8 ADCASEQSR Register (Offset = 7h) [reset = 0h] ........................................................... 489

7.4.9 ADCRESULT_0 to ADCRESULT_15 Register (Offset = 8h to 17h) [reset = 0h]........................ 490

7.4.10 ADCTRL3 Register (Offset = 18h) [reset = 0h] ............................................................. 491

7.4.11 ADCST Register (Offset = 19h) [reset = 0h] ................................................................ 492

7.4.12 ADCREFSEL Register (Offset = 1Ch) [reset = 0h]......................................................... 493

7.4.13 ADCOFFTRIM Register (Offset = 1Dh) [reset = 0h] ....................................................... 494

8 Direct Memory Access (DMA) Module ................................................................................ 495

8.1 Introduction ................................................................................................................ 496

8.2 Architecture................................................................................................................ 497

8.2.1 Block Diagram.................................................................................................... 497

8.2.2 Peripheral Interrupt Event Trigger Sources .................................................................. 498

8.2.3 DMA Bus.......................................................................................................... 499

8.3 Pipeline Timing and Throughput........................................................................................ 500

8.4 CPU Arbitration ........................................................................................................... 501

8.4.1 For the External Memory Interface (XINTF) Zones ......................................................... 501

8.4.2 For All Other Peripherals/Memories........................................................................... 502

8.5 Channel Priority ........................................................................................................... 502

8.5.1 Round-Robin Mode.............................................................................................. 502

8.5.2 Channel 1 High Priority Mode.................................................................................. 503

8.6 Address Pointer and Transfer Control ................................................................................. 503

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