没有合适的资源?快使用搜索试试~ 我知道了~
首页SPC5604B/C、MPC5604B/C参考手册
SPC5604B/C、MPC5604B/C参考手册
需积分: 50 29 下载量 49 浏览量
更新于2023-05-09
1
收藏 7.22MB PDF 举报
NXP公司的SPC5604B/C、MPC5604B/C系列芯片的参考手册、该文档中包含寄存器详细内容,可通过文档中的寄存器描述完成单片机的程序开发
资源详情
资源推荐
Freescale Semiconductor
MPC5604BCRM
Rev. 8.2, 09/2013
© Freescale Semiconductor, Inc., 2013. All rights reserved.
MPC5604B/C Microcontroller
Reference Manual
This is the MPC5604B/C Reference Manual set consisting of the following files:
• MPC5604B/C Reference Manual Addendum (MPC5604B/CRMAD), Rev. 2
• MPC5604B/C Reference Manual (MPC5604B/CRM), Rev. 8
Freescale Semiconductor
Reference Manual Addendum
MPC5604BRMAD
Rev. 2, 09/2013
Table of Contents
© Freescale Semiconductor, Inc., 2013. All rights reserved.
This addendum describes corrections to the
MPC5604B/C Microcontroller Reference Manual, order
number MPC5604BCRM. For convenience, the addenda
items are grouped by revision. Please check our website
at http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5604B/C
Microcontroller Reference Manual is Revision 8.1.
MPC5604B/C Microcontroller
Reference Manual Addendum
1 Addendum List for Revision 8.1 . . . . . . . . . . . . . . 2
2 Addendum List for Revision 8 . . . . . . . . . . . . . . . . 2
3 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MPC5604BRMAD, Rev. 2
Freescale Semiconductor2
1 Addendum List for Revision 8.1
2 Addendum List for Revision 8
Table 1. MPC5604BCRM Rev 8.1 Addenda
Location Description
Chapter 27, “Flash Memory”
page 644
Add a note below Table 27-4, “CFlash TestFlash Structure”.
NOTE
Unique Device ID – Memory location. This device now includes a 128-bit Unique
Identification number (UID) which is programmed during device fabrication.
Start – Stop Address Size (Bytes) Content:
• 0x00403C10 0x00403C17 8 UID 1
• 0x00403C18 0x00403C1F 8 UID 2
Table 2. MPC5604BCRM Rev 8 Addenda
Location Description
Chapter 4, Signal description,
page 60
In Table 4-3, Functional port pin descriptions, row PH[9], change the pin numbers for
MPC560xB 64 LQFP and MPC560xC 64 LQFP from “—” to 60.
In row PH[10], change the pin numbers for MPC560xB 64 LQFP and MPC560xC 64 LQFP
from “—” to 53.
Chapter 6, Clock Description,
page 113
Add Note: to Section 6.8.4.1, Crystal clock monitor:
Note: Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is
greater than (FIRC / 2
RCDIV
)+0.5MHz.
Add Note: to Section 6.8.4.2, FMPLL clock monitor:
Note: Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is
greater than (FIRC / 4) + 0.5 MHz.
Chapter 9, Reset Generation
Module (MC_RGM), page
209
Replace Section 9.4.7, Boot Mode Capturing, with the following:
The MC_RGM samples PA[9:8] whenever RESET is asserted until five FIRC (16 MHz internal
RC oscillator) clock cycles before its deassertion edge. The result of the sampling is used at
the beginning of reset PHASE3 for boot mode selection and is retained after RESET has been
deasserted for subsequent boots after reset sequences during which RESET is not asserted.
Note: In order to ensure that the boot mode is correctly captured, the application needs to
apply the valid boot mode value the entire time that RESET is asserted.
RESET can be asserted as a consequence of the internal reset generation. This will force
re-sampling of the boot mode pins. (See Table 9-12 for details.)
Chapter 13, Real Time Clock /
Autonomous Periodic
Interrupt (RTC/API), page
262
In Table 13-3 (RTCC field descriptions), update Note in RTCC[APIVAL] field description:
Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two
more cycles because of synchronization of APIVAL to the RTC clock, and APIVAL + 1 cycles
for subsequent occurrences. After that, interrupts are periodic in nature. Because of
synchronization issues, the minimum supported value of APIVAL is 4.
MPC5604BRMAD, Rev. 2
Freescale Semiconductor 3
Chapter 21, LINFlex, p. 412 Insert the following section:
21.8.2.1.6 Overrun
Once the message buffer is full, the next valid message reception leads to an
overrun and a message is lost. The hardware sets the BOF bit in the LINSR to
signal the overrun condition. Which message is lost depends on the
configuration of the RX message buffer:
• If the buffer lock function is disabled (LINCR1[RBLM] = 0) the last
message stored in the buffer is overwritten by the new incoming
message. In this case the latest message is always available to the
application.
• If the buffer lock function is enabled (LINCR1[RBLM] = 0) the most
recent message is discarded and the previous message is available in the
buffer.
Chapter 22, FlexCAN,
throughout chapter
Remove references throughout the chapter to “low-cost MCUs.”
Chapter 22, FlexCAN, page
429
Add this Note in the RTR field description of Table 22-4 (Message Buffer Structure field
description):
Note: Do not configure the last Message Buffer to be the RTR frame.
Chapter 22, FlexCAN, page
461
In Section 22.4.9.4, Protocol timing, update the Note following Figure 22-16 (CAN engine
clocking scheme) to read: “This clock selection feature may not be available in all MCUs. A
particular MCU may not have a PLL, in which case it would have only the oscillator clock, or
it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit
in the CTRL Register has no effect on the module operation.”
Chapter 22, FlexCAN, page
462
Update the table title of Table 22-20 from “CAN Standard Compliant Bit Time Segment Settings”
to “Bosch CAN 2.0B standard compliant bit time segment settings.”
Chapter 22, FlexCAN, page
463
In Section 22.4.9.4, Protocol timing, update the Note following Table 22-20 to read: “Other
combinations of Time Segment 1 and Time Segment 2 can be valid. It is the user’s
responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit
time calculations, use an IPT (Information Processing Time) of 2, which is the value
implemented in the FlexCAN module.”
Chapter 25, Analog-to-Digital
Converter (ADC), page
In Section 28.3.5.2, Presampling channel enable signals, in Table 28-7, Presampling voltage
selection based on PREVALx fields, in the 01 row, change the “Presampling voltage” field to:
V1 = V
DD_HV_ADC0
or V
DD_HV_ADC1
.
Chapter 25, Analog-to-Digital
Converter (ADC), page 597
In Section 25.3.2, Analog clock generator and conversion timings, remove the paragraph:
The direct clock should basically be used only in low power mode when the device is using
only the 16 MHz fast internal RC oscillator, but the conversion still requires a 16 MHz clock
(an 8 MHz clock is not fast enough). In all other cases, the ADC should use the clock divided
by two internally.
Table 2. MPC5604BCRM Rev 8 Addenda
Location Description
MPC5604BRMAD, Rev. 2
Freescale Semiconductor4
3 Revision History
Table 3 provides a revision history for this reference manual addendum document.
Chapter 25, Analog-to-Digital
Converter (ADC), p. 600
In Section 25.3.4.2, CTU in trigger mode, replace the sentence:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded.
with:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded. However, if the CTU has triggered a conversion that is still ongoing on a channel,
it will buffer a second request for the channel and wait for the end of the first conversion before
requesting another conversion. Thus, two conversion requests close together will both be
serviced.
Chapter 25, Analog-to-Digital
Converter (ADC), page 603
Add Note to Section 25.3.10, Auto-clock-off mode:
Note: The auto-clock-off feature cannot operate when the digital interface runs at the same
rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock
will not shut down in IDLE mode.
Chapter 25, Analog-to-Digital
Converter (ADC), page 610
In Section 25.4.6.2, Main Status Register (MSR), replace the ADCSTATUS field description with
the following:
The value of this parameter depends on ADC status:
000 IDLE — The ADC is powered up but idle.
001 Power-down — The ADC is powered down.
010 Wait state — The ADC is waiting for an external multiplexer. This occurs only when the
DSDR register is nonzero.
011 Reserved
100 Sample — The ADC is sampling the analog signal.
101 Reserved
110 Conversion — The ADC is converting the sampled signal.
111 Reserved
Chapter 26, Cross Triggering
Unit (CTU), page 633
At the end of Section 26.4.1, Event Configuration Registers (CTU_EVTCFGRx) (x = 0...63), add
the following Note:
NOTE
The CTU tracks issued conversion requests to the ADC. When the ADC
is being triggered by the CTU and there is a need to shut down the ADC,
the ADC must be allowed to complete conversions before being shut
down. This ensures that the CTU is notified of completion; if the ADC
is shut down while performing a CTU-triggered conversion, the CTU is
not notified and will not be able to trigger further conversions until the
device is reset.
Table 3. Revision History Table
Rev. Number Substantive Changes Date of Release
2.0 Add a note below Table 27-4, “CFlash TestFlash Structure” 09/2013
1.0 Initial release. 05/2012
Table 2. MPC5604BCRM Rev 8 Addenda
Location Description
剩余933页未读,继续阅读
大橙子疯
- 粉丝: 1526
- 资源: 12
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- 中文翻译Introduction to Linear Algebra, 5th Edition 2.1节
- zigbee-cluster-library-specification
- JSBSim Reference Manual
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功