________________________________________________________________________
Compact
PCI System Management Specification Draft 01/21/2000
Do Not Claim Conformance to This Specification
3
Table of Contents
1. Overview (Environment).......................................................................................................................... 6
1.1 Description and Goals of the Specification ...................................................................................... 6
1.2 Justification....................................................................................................................................... 6
1.3 Using this Specification.................................................................................................................... 7
1.3.1 The Developers....................................................................................................................... 7
1.3.2 The I
2
C bus and capacitive loading......................................................................................... 8
1.3.3 Hot-swap................................................................................................................................. 9
1.3.4 The BMC ................................................................................................................................ 9
1.3.5 Intelligent versus non-intelligent devices............................................................................. 10
1.4 Definitions...................................................................................................................................... 10
1.5 Supporting Documents ................................................................................................................... 11
2. Electrical Characteristics....................................................................................................................... 13
2.1 Standard Node................................................................................................................................ 13
2.1.1 Standard Node Parameters.................................................................................................... 13
2.1.2 Hot-swap Capability.............................................................................................................. 14
2.1.2.1 Initialization.........................................................................................................................................14
2.1.2.2 Signal Transient Rejection...................................................................................................................14
2.1.2.3 Transmission Violations......................................................................................................................14
2.1.2.4 Protocol Violations..............................................................................................................................15
2.1.3 Node Power........................................................................................................................... 15
2.2 Non-Standard Node........................................................................................................................ 16
2.3 Management Bus Topology............................................................................................................ 16
2.3.1 Line Loading Limitations...................................................................................................... 16
2.3.2 Line Biasing Requirements................................................................................................... 17
3. System Management Requirements...................................................................................................... 18
3.1 Chassis............................................................................................................................................ 18
3.1.1 Backplane.............................................................................................................................. 18
3.1.1.1 IPMB 0................................................................................................................................................18
3.1.1.2 IPMB 1................................................................................................................................................18
3.1.1.3 Treatment of ALERT#.........................................................................................................................19
3.1.1.4 IPMB Extension connector..................................................................................................................19
3.1.2 System Management Power.................................................................................................. 19
3.1.3 Bridging and Extending ........................................................................................................ 20
3.2 System Board Computer and BMC................................................................................................20
3.2.1 Baseboard Management Controller....................................................................................... 21
3.2.1.1 System Interface ..................................................................................................................................21
3.2.1.2 Single-ported IPMB.............................................................................................................................21
3.2.1.3 Dual-ported IPMB...............................................................................................................................21
3.2.1.4 Optional and Private Busses................................................................................................................22
3.2.1.5 Repository Storage ..............................................................................................................................22
3.2.1.6 IPMI Compatibility and Interoperability .............................................................................................22
3.2.2 BMC Deployment................................................................................................................. 23
3.2.2.1 BMC Power.........................................................................................................................................23
3.2.2.2 System Interface ..................................................................................................................................23
3.2.2.3 Single-ported BMC..............................................................................................................................23
3.2.2.4 Dual-ported BMC................................................................................................................................23
3.2.2.5 Ancillary BMC Support.......................................................................................................................23
3.3 Address Allocation for Peripherals................................................................................................. 24
3.3.1 General Allocation Principles ............................................................................................... 24
3.3.2 Programmatic Allocation of Peripheral Addresses ............................................................... 24
3.3.2.1 Power Supply Management Node Address Mapping ..........................................................................25
3.3.2.2 CompactPCI Peripheral Management Node Address Mapping...........................................................25
3.4 CompactPCI peripheral cards......................................................................................................... 26
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