UltraScale Architecture PCB Design 5
UG583 (v1.16) June 26, 2019 www.xilinx.com
04/09/2018 1.12 Chapter 1: Added PCB Decoupling Capacitors for Virtex UltraScale+ High
Bandwidth Memory Devices.
Chapter 3: Added new chapter.
Chapter 4: In last bullet of SD/SDIO, changed CMD3 to DAT3. Updated second
paragraph in Unconnected V
CCO Pins
.
Appendix B: Added new appendix.
Appendix C: Added DS926 and PG269 to References.
02/22/2018 1.11 Reorganized content between Chapter 1, Chapter 4, Chapter 6, and Chapter 7.
Chapter 1: Updated first paragraph in Recommended PCB Capacitors per Device
and added bullet item to resource usage list. Added
ideal value of 0.47 µF to
Table 1-14. Added Recommended Decoupling Capacitor Quantities for Kintex
UltraScale and Virtex UltraScale Devices, Recommended Decoupling Capacitor
Quantities for Kintex UltraScale+ and Virtex UltraScale+ Devices, and Recommended
Decoupling Capacitor Quantities for Zynq UltraScale+ Devices. Moved and updated
Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs from
Chapter 7.
Updated Table 1-20 .
Chapter 2: Rewrote Overview. In Table 2 - 1, updated descriptions of L2, L4, L13,
and L15 layers. In General Memory Routing Guidelines, removed description of
maximum routing length in guideline 2, and updated guidelines 5, 6, 14, and 23.
Added Figure 2-13. Reversed order of PCB Guidelines for DDR3/3L SDRAM (PL and
PS) and PCB Guidelines for DDR4 SDRAM (PL and PS) sections. Removed Table
2-11: PCB Guidelines for DDR4 SDRAM and Table 2-22: PCB Guidelines for DDR3
SDRAM. In Table 2-20 , Table 2-22 , Table 2 -11, Ta b l e 2 - 1 5 , Tab l e 2 - 2 7 to Table 2 - 2 9,
updated L0 and L1 trace lengths, and added note 2. In Ta b l e 2-2 1 , Tabl e 2-1 3 , and
Table 2 -26 , updated L0 and L1 trace lengths, and note 2. Updated skew constraints
for signal group data to DQS in Ta b le 2 -24, Tabl e 2-1 7 , Ta b le 2 - 31, and Table 2-34 .
Updated note after Table 2 - 25. Added alert_n to Table 2 -9. Added note to Fly-by
and Clamshell Topologies. Added note to Tab l e 2 -1 0 . Added alert_n. Updated
Figure 2-23. In Table 2 -1 2 and Ta b le 2 - 14, updated L0 and L1 trace lengths, and
added note 1. Updated note after Ta b le 2 - 1 8, Table 2-32 , Ta b le 2 - 35, Tab l e 2- 7 8 ,
Table 2 -85 , and Ta b le 2 - 90. Added Tabl e 2-4 6 . Added Signal Segment column to
Table 2 -69 . Updated L1 trace length in Ta b l e 2 - 71, Tabl e 2-7 2 ,
Table 2 -74 to
Table 2 -76 , Ta b le 2 - 8 3, Ta b l e 2-8 7 , and Table 2 - 88. Added VREFCA and VREFDQ.
Removed instances of length constraints from introductory text in RLDRAM 3
Memory Routing Constraints, including Tab l e 2- 7 7 . Removed skew constraints
(mil) column from Ta bl e 2 - 78 . Added PCB Guidelines for LPDDR4 Memories
without ECC (PS), PCB Guidelines for LPDDR4 Memories with ECC (PS), and PCB
Guidelines for LPDDR3 SDRAM (PL and PS) from Chapter 4.
Chapter 4: Renamed chapter title. Removed section Design Example for x32
LPDDR4 with ECC. In CAN, changed PCB and package skew to ±100 ps. Added
bullet about series resistor to eMMC. In Standard and High-Speed SDR Interfaces,
updated heading and changed PCB and package skew to ±100 ps. Updated
heading in HS200 (200 MHz) and High-Speed DDR Interfaces. Removed TDO from
JTAG. In SDR Mode, changed PCB and package skew to ±100 ps. In DDR Mode
(100 MHz), updated second bullet and added third bullet. In PS Reset (External
System Reset and POR Reset), replaced VCCO_PSIO[3] with VCCO_MIO0 in first
bullet, and added two new bullets. Updated first and second bullets in PS_INIT_B,
PS_PROG_B, and PS_DONE. Updated fifth bullet in QSPI. Updated first bullet in
Real-Time Clock. In SD/SDIO, updated first bullet, removed bullet about PCB and
package delay skew, and added bullet about 10 kΩ pull-up resistor. In SPI, Triple
Time Counter, and Watchdog Timer, changed PCB and package skew to ±100 ps.
Date Version Revision
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