UltraScale架构FPGA与DDR4内存接口的PCB设计指南

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"FPGA-DDR4-ultrascale-pcb-design.pdf" 这是一份关于Xilinx UltraScale架构在PCB设计中的应用指南，特别关注DDR4 SDRAM的接口设计。文档详细介绍了如何优化信号完整性，确保高速数据传输的可靠性。在DDR3 SDRAM的设计中，地址、命令和控制信号采用飞跨（Fly-by）拓扑结构进行终止处理。这种拓扑是为了应对高速信号传输带来的挑战，以提高信号质量。每一路地址、命令或控制信号都直接在同层布线，从相应的UltraScale设备引脚一直延伸到远端终结，除了在分岔区域。这意味着每个单独的信号路由都不应被分割到多个层面上，以减少信号反射和干扰，从而实现最佳的信号完整性。图2-27展示了DDR3 SDRAM的地址飞跨终止方式。在这样的设计中，信号线沿单一路径连续布设，减少了信号在不同层之间切换产生的额外延迟和信号质量下降。这种方法对于维持DDR3 SDRAM高速数据传输时的稳定性和可靠性至关重要。文档还提到了 UltraScale架构的PCB设计指南，包括推荐的PCB电容配置、步骤负载假设的更新、表格的修订以及对VCC_PSDDR_PLL Supply中电容值和部分编号的更新。例如，增加了10μF 0402和47μF 0603电容的部分编号，同时删除了针对Virtex UltraScale+ 58G启用设备和Virtex UltraScale+高带宽内存设备的PCB去耦电容部分，转而提供了更具体的电容规格。在第二章中，表2-3和图2-5得到了更新，添加了VRP(PL)和ZQ(PS)到表2-9和表2-19，以及图2-31至图2-36的电源参考。此外，还引入了reset_n信号，并移除了关于引脚终结的注释，这可能意味着在最新的设计中，reset_n信号的处理有所变化，对系统复位管理有更精确的要求。这份文档的修订历史表明，截至2019年6月26日，文档版本为1.16，进行了多次更新以反映最新的设计建议和技术改进，确保与Xilinx UltraScale FPGA平台的DDR4接口设计保持同步，以满足高性能计算和数据处理应用的需求。

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UltraScale Architecture PCB Design 16

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Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Possibility 1: Excessive Noise from Other Devices on the PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

Possibility 3: I/O Signals in PCB are Stronger Than Necessary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

Chapter 12: Design of Transitions for High-Speed Signals

Excess Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Time Domain Reflectometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

SMT Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Differential Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

P/N Crossover Vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

SMA Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Backplane Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Microstrip/Stripline Bends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Appendix A: Memory Derating Tables

Appendix B: Material Properties and Insertion Losses

Appendix C: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

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Chapter 1

Power Distribution System in

UltraScale Devices

Introduction to UltraScale Architecture

The Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enable multi-

hundred gigabit-per-second levels of system performance with smart processing, while

efficiently routing and processing data on-chip. UltraScale architecture-based devices

address a vast spectrum of high-bandwidth, high-utilization system requirements by using

industry-leading technical innovations, including next-generation routing, ASIC-like

clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power

reduction features. The devices share many building blocks, providing scalability across

process nodes and product families to leverage system-level investment across platforms.

Virtex® UltraScale+™ devices provide the highest performance and integration capabilities

in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as

well as the highest on-chip memory density. As the industry's most capable FPGA family,

the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and

data center and fully integrated radar/early-warning systems.

Virtex UltraScale devices provide the greatest performance and integration at 20 nm,

including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA at

the 20 nm process node, this family is ideal for applications including 400G networking,

large scale ASIC prototyping, and emulation.

Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET

node, delivering the most cost-effective solution for high-end capabilities, including

transceiver and memory interface line rates as well as 100G connectivity cores. Our newest

mid-range family is ideal for both packet processing and DSP-intensive functions and is well

suited for applications including wireless MIMO technology, Nx100G networking, and data

center.

Kintex UltraScale devices provide the best price/performance/watt at 20 nm and include

the highest signal processing bandwidth in a mid-range device, next-generation

transceivers, and low-cost packaging for an optimum blend of capability and cost-

effectiveness. The family is ideal for packet processing in 100G networking and data centers

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Chapter 1: Power Distribution System in UltraScale Devices

applications as well as DSP-intensive processing needed in next-generation medical

imaging, 8k4k video, and heterogeneous wireless infrastructure.

Zynq® UltraScale+ MPSoC devices provide 64-bit processor scalability while combining

real-time control with soft and hard engines for graphics, video, waveform, and packet

processing. Integrating an Arm®-based system for advanced analytics and on-chip

programmable logic for task acceleration creates unlimited possibilities for applications

including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.

This user guide describes the UltraScale architecture PCB design and pin planning resources

and is part of the UltraScale Architecture documentation suite available at:

www.xilinx.com/ultrascale.

Introduction

This chapter documents the power distribution system (PDS) for UltraScale devices,

including decoupling capacitor selection, placement, and PCB geometries. A simple

decoupling method is provided for each device. Basic PDS design principles are covered, as

well as simulation and analysis methods. This chapter contains the following sections:

• PCB Decoupling Capacitors

• Transceiver PCB Routing Guidelines

• Maximum Current Draw for V

CCINT in Virtex UltraScale+ Devices

PCB Decoupling Capacitors

Recommended PCB Capacitors per Device

Recommended decoupling capacitor quantities for Kintex UltraScale and Virtex UltraScale

devices are listed in Tabl e 1- 2 and Ta ble 1-3 . Decoupling capacitor quantities for

Kintex UltraScale+ and Virtex UltraScale+ devices are listed in Table 1-4 and Tabl e 1- 5 .

Decoupling capacitor quantities for Zynq UltraScale+ devices are listed in Tab le 1-9 . The

optimized quantities of PCB decoupling capacitors assume that the voltage regulators have

stable output voltages and meet the regulator manufacturer's minimum output capacitance

requirements.

The assumptions used for the decoupling quantities are shown below. If any of those

assumptions significantly differ from the actual design, simulations are recommended to

determine the actual amount of required capacitance, which could be higher or lower. The

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Chapter 1: Power Distribution System in UltraScale Devices

decoupling recommendations are designed for optimal performance between roughly

100 kHz and 10–20 MHz.

Because device capacitance requirements vary with CLB and I/O utilization, PCB decoupling

guidelines are provided on a per-device basis based on very high utilization so as to cover

a majority of use cases. Resource usage consists (in part) of:

• 80% of LUTs and registers at 245 MHz and 25% toggle rate

• 80% block RAM and DSP at 491 MHz and 50% toggle rate

• 50% MMCM and 25% PLL at 500 MHz

• 25% I/O at SSTL 1.2/1.35 at 1200 MHz and 40% toggle rate

• 75% I/O at POD 1.2 at 1200 MHz DDR and 40% toggle rate

An importable XPE file that contains the above usage assumptions in a KU9P FFVE900

device can be downloaded from the Xilinx website.

Step Load Assumptions

Different step loads are assumed for each main voltage rail. The step load is the percentage

of the dynamic current that is expected to be demanded at any given switching event.

Tab l e 1- 1 lists the step load percentage used when calculating device capacitance

requirements.

The slew rate of the switching event is dependent on the design, and can be estimated to be

between 1 ns and 100 ns (or longer). Smaller current designs generally have faster current

slew rates, while larger designs tend to have slower slew rates. A general rule of thumb for

high-current designs can be considered to be 0.25 ns per amp (or 4 A/ns) of step current.

The Xilinx Power Estimator (XPE) tool is used to estimate the current on each power rail.

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 1]

and Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 2]

provide the operating range for all the various power rails. The PCB designer should ensure

that the AC ripple plus the DC tolerance of the voltage regulator do not exceed the

operating range.

The capacitor numbers shown in this user guide are based on the following assumptions:

Table 1-1: Step Load for Device Capacitance

Voltage Rail Step Load (%)

CCINT

CCINT_IO

CCBRAM

CCAUX

CCAUX_IO

100

CCO

(HP/HR) 100

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Chapter 1: Power Distribution System in UltraScale Devices

CCINT

operating range from the data sheet = 3%;

Assumed DC tolerance = 1%;

Therefore, allowable AC ripple = 3% – 1% = 2%.

The target impedance is calculated using the 2% AC ripple along with the current estimates

from XPE for the above resource utilization to arrive at the capacitor recommendations. The

equation for target impedance is:

Equation 1-1

CCINT

, V

CCAUX

, and V

CCBRAM

capacitors are listed as the quantity per device, while V

CCO

capacitors are listed as the quantity per I/O bank. Device performance at full utilization is

equivalent across all devices when using these recommended networks.

Tab l e 1- 2 through Tab le 1-9 do not provide the decoupling networks required for the GTY

or GTH transceiver power supplies. For this information, refer to the UltraScale Architecture

GTH Transceivers User Guide (UG576) [Ref 6] or the UltraScale Architecture GTY Transceivers

User Guide (UG578) [Ref 7].

RECOMMENDED: Refer to the UltraScale Architecture Schematic Review Checklist (XTP344) [Ref 8] and

UltraScale+ FPGA and Zynq UltraScale+ MPSoC Schematic Review Checklist (XTP427) [Ref 18] for a

comprehensive checklist for schematic review which complements this user guide.

Note: The capacitor values and part numbers have been updated taking into account the latest

product offerings from various vendors because some of the part numbers from the previous

versions of this user guide have reached end of life. The new guidelines also incorporate capacitors

with a wider temperature range (X6S) compared to the previous part numbers, while moving away

from a combination of tantalum/ceramic capacitors to solely ceramic capacitors across the entire

frequency range. The prior capacitor tables and specifications are still valid for existing designs, but

for new designs, the current tables and specifications are recommended.

Recommended Decoupling Capacitor Quantities for Kintex

UltraScale and Virtex UltraScale Devices

Tab l e 1- 2 and Ta b le 1 -3 show the recommended decoupling capacitor quantities for Kintex

UltraScale and Virtex UltraScale devices.

target

VoltageRailValue

% Ripple

100

-----------------------

StepLoadCurrent

--------------------------------------------------------------------------=

Table 1-2: Kintex UltraScale Devices Decoupling Capacitor Recommendations

CCINT

CCINT_IO

(1)

CCBRAM

CCAUX

CCAUX_IO

(2)

HRIO/HPIO

(3)

(per bank)

330 µF 100 µF 47 µF 10 µF 47 µF 10 µF 47 µF 10 µF 47 µF 10 µF

XCKU025-FFVA1156 1 4 1 1 1 1 1 1 1 1

XCKU035-FBVA676 1 5 1 1 1 1 1 1 1 1

XCKU035-SFVA784 1 5 1 1 1 1 1 1 1 1

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