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Introduction to MIPI DSI
Display Serial Interface
21 September 2005
DWG Display Working Group
Dick Lawrence, Chair

Legal Disclaimer
The material contained herein is not a license, either expressly or impliedly, to any IPR
owned or controlled by any of the authors or developers of this material or MIPI.
The material contained herein is provided on an “AS IS” basis and to the maximum
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MIPI Alliance Confidential

A Very Short Introduction:
Display Architectures
Two Basic Architectures
Video-mode displays (example: DPI, DPI-2)
•
Display Bus traffic is streaming pixels, directly to LCD panel
•
Frame Buffer and Timing Control is in the host processor
Command-mode displays (example: DBI, DBI-2)
•
Frame Buffer, display Timing Controller on Display Panel
•
Display Bus traffic is commands and updates to frame buffer (e.g. video)
Display Command Set (DCS)
•
Standardized set of commands for Command-Mode displays
•
Requires both READ and WRITE cycles to display registers, frame buffer
•
Power control, read Descriptor Block, more

Display Architecture – Video Mode
Display
Driver
Host
Processor
Display Panel
LCD
Display
Bus
Interface
Bus
Interface
Color
Frame
Buffer
Display Refresh
Timing
Control
Update
Frame
Buffer

Display Architecture – Command Mode
Host
Processor
Display Panel
LCD
Display
Bus
Interface
Color
Frame
Buffer
Image
Update
Data
Commands &
Image Update
Data
Bus
Interface
Display Controller
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