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ultrascale器件选型指南
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最新ultrascale器件选型指南 ultrascale-fpga-product-selection-guide
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© Copyright 2013–2016 Xilinx
.

© Copyright 2013–2016 Xilinx
.
Page 2
Kintex® UltraScale™ FPGAs
Device Name
KU025
(1)
KU035 KU040 KU060 KU085 KU095 KU115
Logic Resources
System Logic Cells (K)
318 444 530 726 1,088
1,176
1,451
CLB Flip-
Flops
290,880 406,256 484,800 663,360
995,040 1,075,200
1,326,720
CLB LUTs
145,440 203,128 242,400 331,680
497,520 537,600
663,360
Memory Resources
Maximum Distributed RAM
(Kb)
4,230 5,908 7,050 9,180
13,770 4,800
18,360
Block RAM/FIFO w/ECC (36Kb
each)
360 540 600 1,080
1,620 1,680
2,160
Block RAM/FIFO (18Kb
each)
720 1,080 1,200 2,160
3,240 3,360
4,320
Total Block RAM
(Mb)
12.7 19.0 21.1 38.0
56.9 59.1
75.9
Clock Resources
CMT (1 MMCM, 2
PLLs)
6 10 10 12
22 16
24
I/O DLL
24 40 40 48
56 64
64
I/O Resources
Maximum Single-
Ended HP I/Os
208 416 416 520
572 650
676
Maximum Differential HP I/O Pairs
96 192 192 240
264 288
312
Maximum Single-
Ended HR I/Os
104 104 104 104
104 52
156
Maximum Differential HR I/O Pairs
48 48 48 48
56 24
72
Integrated IP
Resources
DSP Slices
1,152 1,700 1,920 2,760
4,100 768
5,520
System Monitor
1 1 1 1
2 1
2
PCIe® Gen1/2/3
1 2 3 3
4 4
6
Interlaken
0 0 0 0
0 2
0
100G Ethernet
0 0 0 0
0 2
0
16.3Gb/s Transceivers (GTH/GTY)
12 16 20 32
56 64
(2)
64
Speed Grades
Commercial
-1 -1 -1 -1
-1 -1
-1
Extended
-2 -2 -3 -2 -3 -2 -3
-2 -3 -2
-2 -3
Industrial
-1 -2 -1 -1L -2 -1 -1L -2 -1 -1L -2
-1 -1L -2 -1 -2
-1 -1L -2
Package
Footprint
(3, 4, 5, 6)
Package Dimensions
(mm)
HR I/O, HP I/O, GTH/GTY
A784
(7)
23x23
(8)
104, 364, 8 104, 364, 8
A676
(7)
27x27 104, 208, 16 104, 208, 16
A900
(7)
31x31 104, 364, 16 104, 364, 16
A1156 35x35 104, 208, 12 104, 416, 16 104, 416, 20 104, 416, 28 52, 468, 28
A1517 40x40
104, 520, 32 104, 520, 48
104, 520, 48
Footprint
Compatible with
Virtex® UltraScale
Devices
C1517 40x40 52, 468, 40
D1517 40x40 104, 234, 64
B1760 42.5x42.5
104, 572, 44
52, 650, 48 104, 598, 52
A2104 47.5x47.5 156, 676, 52
B2104 47.5x47.5 52, 650, 64 104, 598, 64
D1924 45x45 156, 676, 52
F1924 45x45 104, 520, 56 104, 624, 64
Notes:
1. Certain advanced configuration features are not supported in the KU025. Refer to the Configuring FPGAs section in DS890, UltraScale Architecture and Product Overview.
2. GTY transceivers in KU095 devices support data rates up to 16.3Gb/s.
3. Packages with the same package footprint designator, e.g., A2104, are footprint compatible with all other UltraScale devices with the same sequence. See the migration table for details on inter-family migration.
4. Maximum achievable performance is device and package dependent; consult the associated data sheet for details.
5. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
6. See UG575, UltraScale Architecture Packaging and Pinouts User Guide for more information.
7. GTH transceivers in A784, A676, and A900 packages support data rates up to 12.5Gb/s.
8. 0.8mm ball pitch. All other packages listed 1mm ball pitch.

© Copyright 2013–2016 Xilinx
.
Page 3
Virtex® UltraScale™ FPGAs
Device Name
XCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU440
Logic Resources
System Logic Cells (K)
783 975 1,176 1,567 2,027 2,350 5,541
CLB Flip-
Flops
716,160 891,424 1,075,200 1,432,320 1,852,800 2,148,480 5,065,920
CLB LUTs
358,080 445,712 537,600 716,160 926,400 1,074,240 2,532,960
Memory Resources
Maximum Distributed RAM (Kb)
4,830 3,980 4,800 9,660 12,690 14,490 28,710
Block RAM/FIFO w/ECC (36Kb
each)
1,260 1,421 1,728 2,520 3,276 3,780 2,520
Block RAM/FIFO (18Kb
each)
2,520 2,842 3,456 5,040 6,552 7,560 5,040
Total Block RAM (Mb)
44.3 50.0 60.8 88.6 115.2 132.9 88.6
Clock Resources
CMT (1 MMCM, 2 PLLs)
10 16 16 20 28 30 30
I/O DLL
40 64 64 80 120 120 120
Transceiver Fractional
PLL
5 8 8 10 13 15 0
I/O Resources
Maximum Single-
Ended HP I/Os
468 780 780 780 650 650 1,404
Maximum Differential HP I/O Pairs
216 360 360 360 300 300 648
Maximum Single-
Ended HR I/Os
52 52 52 52 52 52 52
Maximum Differential HR I/O Pairs
24 24 24 24 24 24 24
Integrated IP
Resources
DSP Slices
600 672 768 1,200 1,560 1,800 2,880
System Monitor
1 1 1 2 3 3 3
PCIe® Gen1/2/3
2 4 4 4 4 6 6
Interlaken
3 6 6 6 8 9 0
100G
Ethernet
3 4 4 6 9 9 3
GTH 16.3Gb/s
Transceivers
20 32 32 40 52 60 48
GTY 30.5Gb/s
Transceivers
20 32 32 40 52 60 0
Speed Grades
Commercial
– – – – – – -1
Extended
-1H -2 -3 -1H -2 -3 -1H -2 -3 -1H -2 -3 -1H -2 -3 -1H -2 -3 -2 -3
Industrial
-1 -2 -1 -2 -1 -2 -1 -2 -1 -2 -1 -2 -1 -2
Package
Footprint
(1, 2, 3)
Package Dimensions
(mm)
HR I/O, HP I/O, GTH 16.3Gb/s, GTY 30.5Gb/s
Footprint
Compatible with
Kintex® UltraScale
Devices
C1517 40x40
52, 468, 20, 20 52, 468, 20, 20 52, 468, 20, 20
D1517 40x40 52, 286, 32, 32 52, 286, 32, 32 52, 286, 40, 32
B1760 42.5x42.5
52, 650, 32, 16 52, 650, 32, 16
52, 650, 36, 16
A2104 47.5x47.5
52, 780, 28, 24 52, 780, 28, 24
52, 780, 28, 24
B2104 47.5x47.5
52, 650, 32, 32 52, 650, 32, 32 52, 650, 40, 36
52, 650, 40, 36 52, 650, 40, 36
C2104 47.5x47.5 52, 364, 32, 32 52, 364, 40, 40
52, 364, 52, 52 52, 364, 52, 52
B2377 50x50 52, 1248, 36, 0
A2577 52.5x52.5 0, 448, 60, 60
A2892 55x55
52, 1404, 48, 0
Notes:
1. Packages with the same package footprint designator, e.g., A2104, are footprint compatible with all other UltraScale devices with the same sequence. See the migration table for details on inter-family migration.
2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
3. See UG575, Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts User Guide for more information.
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