Zynq‐7000EPPTechnicalReferenceManual www.xilinx.com 5
UG585(v1.2)August8,2012
Chapter 3: ApplicationProcessingUnit
3.1 Introduction .............................................. ...................51
3.1.1 BasicFunctionality ...................................................................51
3.1.2 System‐levelView ............. ..................
.....................................53
3.2 CortexA9Processors ..........................................................55
3.2.1 Summary...........................................................................55
3.2.2 C entralProcessingUnit(CPU)......................
....................................55
3.2.3 Level1Caches .............
..........................................................58
3.2.4 MemoryManagementUnit(MMU) .......................................
..............60
3.2.5 Interfaces ... ..................................
............... .......................63
3.2.6 NEON............
................................... ...............................64
3.2.7 PerformanceMonitoringUnit ..................................
........................65
3.3 SnoopControlUnit(SCU)....... ................................................65
3.3.1 Summary...........................................................................65
3.3.2 AddressFiltering .........................
....................................... .....66
3.3.3 SCUMasterPorts ....
................................................................66
3.4 L2‐Cache ..... .... ...........................................................66
3.4.1 Summary...........................................................................66
3.4.2 ExclusiveL2‐L1CacheConfiguration .............. ........
...............................70
3.4.3 CacheReplacementStrategy ..................
.........................................71
3.4.4 CacheLockdown .........
....................................... .....................71
3.4.5 EnablingandDisablingtheL2CacheController .. .................................
.........72
3.4.6 RAMAccessLatencyControl......................................
.....................73
3.4.7 StoreBufferOperation ............................
............... .....................73
3.4.8 OptimizationsBetweenCortex‐A9andL2Controller ........
............... ................74
3.4.9 Pre‐fetchingOperation................. .
............... ...............................75
3.4.10 ProgrammingModel....
...................................... .. .....................76
3.5 APUInterfaces ...............................................................77
3.5.1 PLCo‐processingInterfaces ............................................................77
3.5.2 I nterruptInterface ............... ......................
..............................80
3.6 SupportforTrustZoneWithintheAPU .................................... ........81
3.6.1 CPUSecurityTransition ........... .. ........................................... .......81
3.6.2 CP15RegisterAccessControl ................................
..........................82
3.6.3 MMUSecurity ................ ........
....................................... ........83
3.6.4 L‐1CacheSecurity .
...................................................................83
3.6.5 SecurityExceptionControl ................................
.............................84
3.6.6 CPUDebugTrustZoneAccessControl ..................
..................................84
3.6.7 SCURegisterAccessControl .............
............... ...............................84
3.6.8 TrustZoneSupportintheL2
Cache .................................... .. ................84
3.7 ApplicationProcessingUnit(APU)Reset ..........................................85
3.7.1 ResetFunctionality ............................ .......................................85
3.7.2 APUStateAfterReset............... ................
..................................86
3.8 PowerConsiderations .........................................................86
3.8.1 I ntroduction ......................... ........................................... ....86
3.8.2 StandbyMode ..... .......................
...........................................87
3.8.3 DynamicClockGatingintheL2Controller ..
..............................................87
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