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SPRUHX5F–August 2014–Revised January 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
Contents
3.6.3 PLLSLIP Detection................................................................................................ 99
3.6.4 CPU1 Vector Address Validity Check .......................................................................... 99
3.6.5 NMIWDs .......................................................................................................... 100
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 100
3.6.7 ECC Enabled Flash Memory................................................................................... 100
3.6.8 ERRORSTS Pin.................................................................................................. 100
3.7 Clocking ................................................................................................................... 100
3.7.1 Clock Sources.................................................................................................... 101
3.7.2 Derived Clocks ................................................................................................... 103
3.7.3 Device Clock Domains .......................................................................................... 104
3.7.4 XCLKOUT......................................................................................................... 105
3.7.5 Clock Connectivity ............................................................................................... 106
3.7.6 Clock Source and PLL Setup .................................................................................. 107
3.8 32-Bit CPU Timers 0/1/2................................................................................................. 110
3.9 Watchdog Timers ......................................................................................................... 112
3.9.1 Servicing the Watchdog Timer ................................................................................. 112
3.9.2 Minimum Window Check ....................................................................................... 113
3.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 113
3.9.4 Watchdog Operation in Low Power Modes .................................................................. 114
3.9.5 Emulation Considerations ...................................................................................... 114
3.10 Low Power Modes ........................................................................................................ 115
3.10.1 IDLE .............................................................................................................. 115
3.10.2 STANDBY ....................................................................................................... 115
3.10.3 HALT ............................................................................................................. 115
3.10.4 HIB................................................................................................................ 116
3.11 Memory Controller Module .............................................................................................. 118
3.11.1 Functional Description ......................................................................................... 118
3.12 Flash and OTP Memory ................................................................................................. 125
3.12.1 Features.......................................................................................................... 125
3.12.2 Flash Tools ...................................................................................................... 125
3.12.3 Default Flash Configuration ................................................................................... 126
3.12.4 Flash Bank, OTP and Pump .................................................................................. 126
3.12.5 Flash Module Controller (FMC) ............................................................................... 126
3.12.6 Flash and OTP Power-Down Modes and Wakeup......................................................... 127
3.12.7 Flash and OTP Performance.................................................................................. 128
3.12.8 Flash Read Interface ........................................................................................... 129
3.12.9 Erase/Program Flash........................................................................................... 131
3.12.10 Error Correction Code (ECC) Protection ................................................................... 132
3.12.11 Reserved Locations Within Flash and OTP ............................................................... 136
3.12.12 Procedure to Change the Flash Control Registers ....................................................... 136
3.12.13 Flash Pump Ownership Control ............................................................................. 136
3.13 Dual Code Security Module (DCSM)................................................................................... 138
3.13.1 Functional Description ......................................................................................... 138
3.13.2 CSM Impact on Other On-Chip Resources ................................................................. 144
3.13.3 Incorporating Code Security in User Applications.......................................................... 145
3.14 JTAG ....................................................................................................................... 149
3.15 F2837xS System Control Registers .................................................................................... 151
3.15.1 F2837xS System Control Base Addresses.................................................................. 151
3.15.2 CPUTIMER_REGS Registers................................................................................. 152
3.15.3 PIE_CTRL_REGS Registers .................................................................................. 159
3.15.4 WD_REGS Registers .......................................................................................... 211
3.15.5 NMI_INTRUPT_REGS Registers............................................................................. 217
3.15.6 XINT_REGS Registers......................................................................................... 231
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