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ISSCC2020-SC-1.pdf

ISSCC2020

short

course

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2020年ISSCC的short course第一部分，内容Device and Physical Design Considerations for Circuits in FinFET Technology

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ISSCC 2020 Short Course

Device and Physical Design Considerations for

Circuits in FinFET Technology

Alvin Loke

TSMC

aloke@tsmc.com

February 20, 2020

1 of 80

Mainframe

Computing

Personal

Computing

Mobile

Computing

Ubiquitous

Computing

Semiconductor Drivers

Alvin Loke 2 of 80

Hou, TSMC [1] / Wikipedia [2]

ISSCC 2020 Short Course

Product Units

(millions)

1960 1970 1980 1990 20102000 2020 2030

10µm

µm

1.5

µm

1.0

µm

0.8

µm

0.6

µm

0.35

µm

0.25

µm

0.18

µm

0.13

µm

90nm

65nm

45nm

32nm

22nm

14nm

10nm

7nm

5nm

Node

Mobile

HPC

Auto

IoT

0.01

0.1

100

1000

10,000

100,000

FinFET+DTCO

Strain+HKMG

Dennard Scaling

Moore’s Law – Scaling for Density Reduces Cost

Alvin Loke 3 of 80ISSCC 2020 Short Course

Wong, TSMC [3] / Cai, TSMC [4]

Inverter

SRAM

Logic gates

Transistors

(microprocessors)

100

10k

100k

10M

Relative Density

10µm

µm

1.5

µm

1.0

µm

0.8

µm

0.6

µm

0.35

µm

0.25

µm

0.18

µm

0.13

µm

90nm

65nm

45nm

32nm

22nm

14nm

10nm

7nm

5nm

1970 1980

1990 2000 2010

2020

Outline

o Road to FinFET

o Technology Scaling Enablers

o Design Realities

o Design Strategies

o What’s Ahead

o Conclusion

Alvin Loke 4 of 80ISSCC 2020 Short Course

Outline

o Road to FinFET

n Dennard Scaling (L

gate

, t

, N, x

, V

Scaling)

n Extending Dennard Scaling – Mechanical Strain & HKMG

n Fully Depleted Device

o Technology Scaling Enablers

o Design Realities

o Design Strategies

o What’s Ahead

o Conclusion

Alvin Loke 5 of 80ISSCC 2020 Short Course

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