Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX6DQCEC
Rev. 3, 02/2014
Package Information
Case FCPBGA 21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
© 2012-2014 Freescale Semiconductor, Inc. All rights reserved.
MCIMX6QxExxxxC
MCIMX6QxExxxxD
MCIMX6DxExxxxC
MCIMX6DxExxxxD
1 Introduction
The i.MX 6Dual and i.MX 6Quad processors represent
Freescale Semiconductor’s latest achievement in
integrated multimedia applications processors. These
processors are part of a growing family of
multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
The i.MX 6Dual/6Quad processors feature Freescale’s
advanced implementation of the quad
ARM
®
Cortex
®
-A9 core, which operates at speeds up to
1 GHz. They include 2D and 3D graphics processors, 3D
1080p video processing, and integrated power
management. Each processor provides a 64-bit
DDR3/LVDDR3/LPDDR2-1066 memory interface and
a number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth
®
, GPS, hard drive, displays,
and camera sensors.
The i.MX 6Dual/6Quad processors are specifically
useful for applications such as the following:
• Netbooks (web tablets)
i.MX 6Dual/6Quad
Applications Processors
for Consumer Products
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Updated Signal Naming Convention . . . . . . . . . . . . 7
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 18
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Power Supplies Requirements and Restrictions . . 31
4.3 Integrated LDO Voltage Regulator Parameters. . . 32
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 46
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 50
4.10 General-Purpose Media Interface (GPMI) Timing. 66
4.11 External Peripheral Interface Parameters . . . . . . . 75
5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 140
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 140
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 141
6 Package Information and Contact Assignments . . . . . . 143
6.1 Updated Signal Naming Convention . . . . . . . . . . 143
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 144
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
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