Vivado FIFO Generator 13.2：技术指南与设计流程

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“pg057-fifo-generator.pdf”是Xilinx Vivado Design Suite的一个文档，主要介绍了FIFO Generator v13.2版本的LogiCORE IP产品指南。这份指南涵盖了FIFO核的基本概念、特性、应用、设计指导、设计流程步骤以及详细示例设计等内容。在FPGA设计中，FIFO（First In First Out，先进先出）存储器常用于数据缓冲和通信接口之间数据流的同步。FIFO Generator提供了两种接口类型：本征接口FIFOs和AXI接口FIFOs。本征接口FIFOs直接与硬件逻辑连接，而AXI接口FIFOs则采用了Xilinx的Advanced eXtensible Interface (AXI)，提供了一种标准的接口来处理高速数据传输。 FIFO Generator v13.2的特性总结包括各种性能指标、资源利用率、端口描述等。性能部分详细列出了FIFO在不同条件下的工作表现，资源利用率章节展示了在实现FIFO核时， FPGA资源如查找表（LUTs）、触发器（FFs）等的消耗情况。端口描述部分解释了FIFO核各个输入和输出信号的功能和用途。设计指导部分提供了使用FIFO Generator的一般性建议，例如初始化FIFO、FIFO的使用和控制、时钟管理、复位处理、实际FIFO深度计算、延迟以及特殊设计考虑等。这些内容对理解如何在具体项目中正确配置和使用FIFO核至关重要。设计流程步骤章节详细介绍了定制和生成本征核心或AXI核心的步骤，包括约束设置、仿真、综合和实现过程。这为开发者提供了完整的流程指导，帮助他们将FIFO核集成到自己的设计中。在详细示例设计章节，用户可以学习如何实施示例设计，以及如何进行仿真验证。测试台部分讨论了测试台功能，以及如何自定义演示测试台，以适应特定的设计需求，并处理可能遇到的消息和警告。这份文档是针对Xilinx Vivado用户的FIFO Generator使用手册，提供了全面的技术信息和支持，对于理解和使用FIFO核进行FPGA设计非常有帮助。

FIFO Generator v13.2 www.xilinx.com 16

PG057 October 4, 2017

Chapter 1: Overview

Using Block RAM FIFOs Versus Built-in FIFOs

The Built-In FIFO solutions are implemented to take advantage of logic internal to the

Built-in FIFO macro. Several features, for example, almost full, almost empty, and so forth

were not implemented because they are not native to the macro and require additional

logic in the logic to implement.

Benchmarking suggests that the advantages the Built-In FIFO implementations have over

the block RAM FIFOs (for example, logic resources) diminish as external logic is added to

implement features not native to the macro. This is especially true as the depth of the

Handshaking  

Data Count   

Programmable Empty/Full

Thresholds



(2)



(2)

First-Word Fall-Through  

Synchronous Reset 

(3)



(4)

Asynchronous Reset 

(5)



(5)



(6)



(5)



(5)



(6)

dout Reset Value  

(7)

ECC  

Embedded or Interconnect



(8)



Embedded and Interconnect



ECC Pipeline Register 

(9)



(9)

Dynamic Power Saving 

(9)



(9)

Notes:

1. Xilinx supports Non-symmetric aspect ratio only for UltraScale devices. (The maximum depth is limited to 8192 in

case of Built-In FIFOs).

2. For built-in FIFOs, the range of Programmable Empty/Full threshold is limited to take advantage of the logic

internal to the macro.

3. Available only for UltraScale devices. The synchronous reset (srst) should be synchronous to wr_clk.

4. Available only for UltraScale devices. The synchronous reset (srst) should be synchronous to clk.

5. Asynchronous reset is optional for all FIFOs built using distributed and block RAM.

6. Asynchronous reset is not supported for UltraScale Built-in FIFOs.

7. dout Reset Value is supported only in common clock built-in FIFOs.

8. Embedded register option for independent clocks built-in FIFO is available only in UltraScale family. See

Embedded Registers in Block RAM and FIFO Macros.

9. UltraScale devices only.

Table 1-3: FIFO Configurations Summary (Cont’d)

FIFO Feature

Independent Clocks Common Clock

Block

RAM

Distributed

RAM

Built-in

FIFO

Block

RAM

Distributed

RAM, Shift

Built-in

FIFO

Send Feedback

FIFO Generator v13.2 www.xilinx.com 19

PG057 October 4, 2017

Chapter 1: Overview

wr_data_count [d:0]

Output

Write Data Count: This bus indicates the number of words

written into the FIFO. The count is guaranteed to never

under-report the number of words in the FIFO, to ensure you

never overflow the FIFO. The exception to this behavior is

when a write operation occurs at the rising edge of wr_clk/

clk, that write operation will only be reflected on

wr_data_count at the next rising clock edge.

If D is less than log2(FIFO depth)-1, the bus is truncated by

removing the least-significant bits.

Note:

wr_data_count is also available for UltraScale devices using

a common clock Block RAM-based FIFO when the Asymmetric Port

Width option is enabled.

wr_ack

Output

Write Acknowledge: This signal indicates that a write

request (wr_en) during the prior clock cycle succeeded.

overflow

Output

Overflow: This signal indicates that a write request (wr_en)

during the prior clock cycle was rejected, because the FIFO

is full. Overflowing the FIFO is not destructive to the

contents of the FIFO.

prog_full_thresh

Input

Programmable Full Threshold: This signal is used to input

the threshold value for the assertion and de-assertion of the

programmable full (prog_full) flag. The threshold can be

dynamically set in-circuit during reset.

You can either choose to set the assert and negate threshold

to the same value (using prog_full_thresh), or you can

control these values independently (using

prog_full_thresh_assert and prog_full_thresh_negate).

prog_full_thresh_assert

Input

Programmable Full Threshold Assert: This signal is used to

set the upper threshold value for the programmable full

flag, which defines when the signal is asserted. The

threshold can be dynamically set in-circuit during reset.

Refer to the Vivado IDE for the valid range of values

(1)

prog_full_thresh_negate

Input

Programmable Full Threshold Negate: This signal is used to

set the lower threshold value for the programmable full flag,

which defines when the signal is de-asserted. The threshold

can be dynamically set in-circuit during reset. Refer to

Vivado IDE for the valid range of values

(2)

injectsbiterr

Input

Injects a single bit error if the ECC feature is used on block

RAMs or built-in FIFO macros.

injectdbiterr

Input

Injects a double bit error if the ECC feature is used on block

RAMs or built-in FIFO macros.

wr_rst_busy Output When asserted, this signal indicates that the write domain is

in reset state.

Note:

Available only for UltraScale device built-in FIFOS.

Notes:

1. For 7 series devices using the Built-in FIFO configuration, this signal is connected to the almostfull signal of the

FIFO18E1/FIFO36E1 primitive.

2. Valid range of values shown in the IDE are the actual values even though they are grayed out for some selections.

Table 1-5: Write Interface Signals for FIFOs with Independent Clocks (Cont’d)

Name Direction Description

Send Feedback

FIFO Generator v13.2 www.xilinx.com 20

PG057 October 4, 2017

Chapter 1: Overview

Table 1-6 defines the read interface signals of a FIFO with independent clocks. Read

interface signals are divided into required signals and optional signals, and all signals are

synchronous to the read clock (rd_clk).

Table 1-6: Read Interface Signals for FIFOs with Independent Clocks

Name

Directio

Description

Required

rd_rst

Input

Read Reset: Synchronous to read clock. When asserted,

initializes all internal pointers, flags and output registers of

read clock domain.

rd_clk

Input

Read Clock: All signals on the read domain are

synchronous to this clock.

dout[m:0]

Output

Data Output: The output data bus is driven when reading

the FIFO.

rd_en

Input

Read Enable: If the FIFO is not empty, asserting this signal

causes data to be read from the FIFO (output on dout).

empty

Output

Empty Flag: When asserted, this signal indicates that the

FIFO is empty. Read requests are ignored when the FIFO is

empty, initiating a read while empty is not destructive to

the FIFO.

Optional

almost_empty

Output

Almost Empty Flag: When asserted, this signal indicates

that the FIFO is almost empty and one word remains in the

FIFO.

prog_empty

(1)

Output

Programmable Empty: This signal is asserted when the

number of words in the FIFO is less than or equal to the

programmable threshold. It is de-asserted when the

number of words in the FIFO exceeds the programmable

threshold.

rd_data_count [c:0]

Output

Read Data Count: This bus indicates the number of words

available for reading in the FIFO. The count is guaranteed

to never over-report the number of words available for

reading, to ensure that you do not underflow the FIFO. The

exception to this behavior is when the read operation

occurs at the rising edge of rd_clk/clk, that read operation

is only reflected on rd_data_count at the next rising clock

edge.

If C is less than log2(FIFO depth)-1, the bus is truncated by

removing the least-significant bits.

Note:

rd_data_count is also available for UltraScale devices using

a common clock Block RAM-based FIFO when the Asymmetric

Port Width option is enabled.

valid

Output

Valid: This signal indicates that valid data is available on

the output bus (dout).

Send Feedback

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Vivado FIFO Generator 13.2：技术指南与设计流程

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