RapidIO_Rev_2.2Specification.pdf

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RapidIO Trade Association

Rev. 2.2, 06/2011

RapidIO

™

Interconnect Specification

Part 1: Input/Output Logical

Specification

RapidIO Trade Association

NO WARRANTY.THE RAPIDIO TRADE ASSOCIATION PUBLISHES THE SPECIFICATION “AS IS”. THE RAPIDIO TRADE

ASSOCIATION MAKES NO WARRANTY, REPRESENTATION OR COVENANT, EXPRESS OR IMPLIED, OF ANY KIND

CONCERNING THE SPECIFICATION, INCLUDING, WITHOUT LIMITATION, NO WARRANTY OF NON INFRINGEMENT, NO

WARRANTY OF MERCHANTABILITY AND NO WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. USER AGREES TO

ASSUME ALL OF THE RISKS ASSOCIATED WITH ANY USE WHATSOEVER OF THE SPECIFICATION. WITHOUT LIMITING THE

GENERALITY OF THE FOREGOING, USER IS RESPONSIBLE FOR SECURING ANY INTELLECTUAL PROPERTY LICENSES OR

RIGHTS WHICH MAY BE NECESSARY TO IMPLEMENT OR BUILD PRODUCTS COMPLYING WITH OR MAKING ANY OTHER

SUCH USE OF THE SPECIFICATION.

DISCLAIMER OF LIABILITY. THE RAPIDIO TRADE ASSOCIATION SHALL NOT BE LIABLE OR RESPONSIBLE FOR ACTUAL,

INDIRECT, SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, LOST

PROFITS) RESULTING FROM USE OR INABILITY TO USE THE SPECIFICATION, ARISING FROM ANY CAUSE OF ACTION

WHATSOEVER, INCLUDING, WHETHER IN CONTRACT, WARRANTY, STRICT LIABILITY, OR NEGLIGENCE, EVEN IF THE

RAPIDIO TRADE ASSOCIATION HAS BEEN NOTIFIED OF THE POSSIBILITY OF SUCH DAMAGES.

Questions regarding the RapidIO Trade Association, specifications, or membership should be forwarded to:

RapidIO Trade Association

12343 Hymeadow, Suite 2-R

(non-US mail deliveries to Suite 3-E)

Austin, TX 78750

512-401-2900 Tel.

512-401-2902 FAX.

RapidIO and the RapidIO logo are trademarks and service marks of the RapidIO Trade Association. All other trademarks are the property of their

respective owners.

Revision History

Revision Description Date

1.1 First public release 03/08/2001

1.2 Technical changes: incorporate Rev. 1.1 errata rev. 1.1.1, errata 3 06/26/2002

1.3 Technical changes: incorporate Rev 1.2 errata 1 as applicable,

the following errata showings:

03-05-00006.001, 03-12-00001.001, 04-02-00001.002

and the following new features showings:

04-05-00005.001

Converted to ISO-friendly templates, re-formatted

02/23/2005

1.3 Removed confidentiality markings for public release 06/07/2005

2.0 Technical changes: errata showings 06-11-00000.001, 06-11-00001.004 06/14/2007

2.0 Removed confidentiality markings for public release 03/06/2008

2.1 Technical changes: errata showing 07-06-00000.010 MM/DD/200Y

2.1 Removed confidentiality markings for public release 08/13/2009

2.2 Technical changes: errata showings 09-09-00001.002, 10-08-00000.003,

10-08-00001.005, Consolidated Comments on 11-01-00000.000

05/05/2011

2.2 Removed confidentiality markings for public release 06/06/2011

Table of Contents

RapidIO Trade Association 3

RapidIO Part 1: Input/Output Logical Specification Rev. 2.2

Chapter 1 Overview

1.1 Introduction........................................................................................................... 11

1.2 Overview............................................................................................................... 11

1.3 Features of the Input/Output Specification........................................................... 12

1.3.1 Functional Features........................................................................................... 12

1.3.2 Physical Features .............................................................................................. 12

1.3.3 Performance Features ....................................................................................... 12

1.4 Contents ................................................................................................................ 13

1.5 Terminology.......................................................................................................... 13

1.6 Conventions .......................................................................................................... 13

Chapter 2 System Models

2.1 Introduction........................................................................................................... 15

2.2 Processing Element Models.................................................................................. 15

2.2.1 Processor-Memory Processing Element Model................................................ 15

2.2.2 Integrated Processor-Memory Processing Element Model .............................. 16

2.2.3 Memory-Only Processing Element Model....................................................... 16

2.2.4 Processor-Only Processing Element................................................................. 17

2.2.5 I/O Processing Element .................................................................................... 17

2.2.6 Switch Processing Element............................................................................... 17

2.3 System Issues........................................................................................................ 18

2.3.1 Operation Ordering........................................................................................... 18

2.3.2 Transaction Delivery......................................................................................... 20

2.3.2.1 Unordered Delivery System Issues............................................................... 20

2.3.2.2 Ordered Delivery System Issues................................................................... 21

2.3.3 Deadlock Considerations.................................................................................. 21

Chapter 3 Operation Descriptions

3.1 Introduction........................................................................................................... 23

3.2 I/O Operations Cross Reference ........................................................................... 24

3.3 I/O Operations....................................................................................................... 24

3.3.1 Read Operations................................................................................................ 25

3.3.2 Write and Streaming-Write Operations............................................................ 25

3.3.3 Write-With-Response Operations..................................................................... 26

3.3.4 Atomic (Read-Modify-Write) Operations ........................................................ 26

3.4 System Operations................................................................................................ 27

3.4.1 Maintenance Operations ................................................................................... 27

3.5 Endian, Byte Ordering, and Alignment ................................................................ 27

4 RapidIO Trade Association

Table of Contents

RapidIO Part 1: Input/Output Logical Specification Rev. 2.2

Chapter 4 Packet Format Descriptions

4.1 Request Packet Formats........................................................................................ 31

4.1.1 Addressing and Alignment ............................................................................... 32

4.1.2 Field Definitions for All Request Packet Formats............................................ 32

4.1.3 Type 0 Packet Format (Implementation-Defined)............................................ 35

4.1.4 Type 1 Packet Format (Reserved) .................................................................... 35

4.1.5 Type 2 Packet Format (Request Class)............................................................. 35

4.1.6 Type 3–4 Packet Formats (Reserved)............................................................... 36

4.1.7 Type 5 Packet Format (Write Class)................................................................. 36

4.1.8 Type 6 Packet Format (Streaming-Write Class)............................................... 37

4.1.9 Type 7 Packet Format (Reserved) .................................................................... 38

4.1.10 Type 8 Packet Format (Maintenance Class)..................................................... 38

4.1.11 Type 9–11 Packet Formats (Reserved)............................................................. 40

4.2 Response Packet Formats ..................................................................................... 40

4.2.1 Field Definitions for All Response Packet Formats ......................................... 40

4.2.2 Type 12 Packet Format (Reserved) .................................................................. 41

4.2.3 Type 13 Packet Format (Response Class) ........................................................ 41

4.2.4 Type 14 Packet Format (Reserved) .................................................................. 42

4.2.5 Type 15 Packet Format (Implementation-Defined).......................................... 42

Chapter 5 Input/Output Registers

5.1 Register Summary................................................................................................. 43

5.2 Reserved Register, Bit and Bit Field Value Behavior .......................................... 44

5.3 Extended Features Data Structure......................................................................... 45

5.4 Capability Registers (CARs) ................................................................................ 47

5.4.1 Device Identity CAR

(Configuration Space Offset 0x0)..................................................................47

5.4.2 Device Information CAR

(Configuration Space Offset 0x4)..................................................................48

5.4.3 Assembly Identity CAR

(Configuration Space Offset 0x8)..................................................................49

5.4.4 Assembly Information CAR

(Configuration Space Offset 0xC).................................................................50

5.4.5 Processing Element Features CAR

(Configuration Space Offset 0x10)................................................................51

5.4.6 Switch Port Information CAR

(Configuration Space Offset 0x14)................................................................52

5.4.7 Source Operations CAR

(Configuration Space Offset 0x18)................................................................53

5.4.8 Destination Operations CAR

(Configuration Space Offset 0x1C)...............................................................54

5.5 Command and Status Registers (CSRs)................................................................ 55

5.5.1 Processing Element Logical Layer Control CSR

(Configuration Space Offset 0x4C)...............................................................55

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