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The Digital Display Working Group Promoters (“DDWG Promoters”) are Intel Corporation, Silicon Image, Inc.,
Compaq Computer Corporation, Fujitsu Limited, Hewlett-Packard Company, International Business
Machines Corporation, and NEC Corporation
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY
WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR
SAMPLE.
The DDWG Promoters disclaim all liability, including liability for infringement of any proprietary rights, relating to use
of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
The DDWG Promoters may have patents and/or patent applications related to the Digital Visual Interface Specification.
The DDWG Promoters intend to make available to the industry an Adopter’s Agreement that will include a limited,
reciprocal, royalty-free license to the electrical interfaces, mechanical interfaces, signals, signaling and coding protocols,
and bus protocols described in, and required by, the Digital Visual Interface Specification Revision 1.0 finalized and
published by the DDWG Promoters. To encourage early adoption, Adopters will be required to return their executed
copy of the Adopter's Agreement during an “Adoption Period” which is within one year after the DVI Specification
Revision 1.0 is first published or within one year after the Adopter first sells products that comply with that
specification, whichever is later. This Adoption Period requirement will give parties ample time to understand the
benefits of becoming an Adopter and encourage them to remember this important step.
Copyright © DDWG Promoters 1999.
*Third-party brands and names are the property of their respective owners.
Acknowledgement
The DDWG acknowledges the concerted efforts of employees of Silicon Image, Inc.
and Molex Inc., who authored major portions of this specification. Both companies
have made a significant contribution by developing and licensing to the industry the
core technologies upon which this industry specification is based; transition
minimized differential signaling (T.M.D.S.) technology from Silicon Image, and
connector technology from Molex.
REVISION HISTORY
02 Apr 99 - 1.0 Initial Specification Release
Digital Visual Interface
Revision 1.0
Page 3 of 76
Acknowledgement......................................................................................................2
REVISION HISTORY ...................................................................................................2
1. Introduction................................................................................................ 5
1.1. Scope and Motivation .......................................................................................5
1.2. Performance Scalability ....................................................................................6
1.2.1. Bandwidth Estimation.................................................................................... 7
1.2.2. Conversion to Selective Refresh................................................................... 8
1.3. Related Documents ..........................................................................................8
1.3.1. VESA Display Data Channel (DDC) Specification ........................................ 8
1.3.2. VESA Extended Display Identification Data (EDID) Specification ................ 8
1.3.3. VESA Video Signal Standard (VSIS) Specification....................................... 8
1.3.4. VESA Monitor Timing Specifications (DMT) ................................................. 9
1.3.5. VESA Generalized Timing Formula Specification (GTF).............................. 9
1.3.6. VESA Timing Definition for LCD Monitors Specification............................... 9
1.3.7. Compatibility with Other T.M.D.S. Based Implementations. ......................... 9
2. Architectural Requirements...................................................................10
2.1. T.M.D.S. Overview..........................................................................................10
2.2. Plug and Play Specification ............................................................................10
2.2.1. Overview...................................................................................................... 10
2.2.2. T.M.D.S. Link Usage Model ........................................................................ 11
2.2.3. High Color Depth Support ........................................................................... 13
2.2.4. Low Pixel Format Support........................................................................... 14
2.2.5. EDID............................................................................................................ 14
2.2.6. DDC............................................................................................................. 15
2.2.7. Gamma........................................................................................................ 15
2.2.8. Scaling......................................................................................................... 15
2.2.9. Hot Plugging................................................................................................ 16
2.2.10. HSync, VSync and Data Enable Required.................................................. 17
2.2.11. Data Formats............................................................................................... 18
2.2.12. Interoperability with Other T.M.D.S. Based Specifications .........................18
2.3. Bandwidth ....................................................................................................... 18
2.3.1. Minimum Frequency Supported .................................................................. 18
2.3.2. Alternate Media ........................................................................................... 19
2.4. Digital Monitor Power Management................................................................19
2.4.1. Link Inactivity Definition............................................................................... 21
2.4.2. System Power Management Requirements................................................ 21
2.4.3. Monitor Power Management Requirements................................................ 21
2.5. Analog.............................................................................................................22
2.5.1. Analog Signal Quality.................................................................................. 22
2.5.2. HSync and VSync Required........................................................................ 22
2.5.3. Analog Timings............................................................................................ 22
2.5.4. Analog Power Management........................................................................ 23
2.6. Signal List........................................................................................................23
3. T.M.D.S. Protocol Specification............................................................. 24
3.1 Overview .........................................................................................................24
3.1.1 Link Architecture.......................................................................................... 24
3.1.2 Clocking....................................................................................................... 24
3.1.3 Synchronization...........................................................................................25
3.1.4 Encoding...................................................................................................... 25
3.1.5 Dual-Link Architecture................................................................................. 25
3.2 Encoder Specification .....................................................................................26
3.2.1 Channel Mapping ........................................................................................ 26
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3.2.2 Encode Algorithm ........................................................................................28
3.2.3 Serialization .................................................................................................30
3.3 Decoder Specification .....................................................................................30
3.3.1 Clock Recovery............................................................................................30
3.3.2 Data Synchronization...................................................................................30
3.3.3 Decode Algorithm ........................................................................................31
3.3.4 Channel Mapping.........................................................................................31
3.3.5 Error Handling..............................................................................................31
3.4 Link Timing Requirements ..............................................................................32
4. T.M.D.S. Electrical Specification............................................................33
4.1. Overview..........................................................................................................33
4.2. System Ratings and Operating Conditions .....................................................35
4.3. Transmitter Electrical Specifications ...............................................................35
4.4. Receiver Electrical Specifications ...................................................................38
4.5. Cable Assembly Specifications.......................................................................39
4.6. Jitter Specifications .........................................................................................39
4.7. Electrical Measurement Procedures ...............................................................40
4.7.1. Test Patterns ...............................................................................................40
4.7.2. Normalized Amplitudes................................................................................40
4.7.3. Clock Recovery............................................................................................40
4.7.4. Transmitter Rise/Fall Time...........................................................................41
4.7.5. Transmitter Skew Measurement..................................................................41
4.7.6. Transmitter Eye ...........................................................................................41
4.7.7. Jitter Measurement......................................................................................42
4.7.8. Receiver Eye ...............................................................................................42
4.7.9. Receiver Skew Measurement......................................................................42
4.7.10. Differential TDR Measurement Procedure ..................................................42
5. Physical Interconnect Specification......................................................43
5.1. Overview..........................................................................................................43
5.2. Mechanical Characteristics .............................................................................43
5.2.1. Signal Pin Assignments...............................................................................43
5.2.2. Contact Sequence .......................................................................................44
5.2.3. Digital-Only Receptacle Connectors............................................................45
5.2.4. Combined Analog and Digital Receptacle Connectors ...............................46
5.2.5. Digital Plug Connectors ...............................................................................47
5.2.6. Analog Plug Connectors..............................................................................47
5.2.7. Recommended Panel Cutout ......................................................................48
5.2.8. Mechanical Performance.............................................................................49
5.3. Electrical Characteristics.................................................................................50
5.3.1. Connector Electrical Performance...............................................................50
5.3.2. Cable Electrical Performance ......................................................................52
5.4. Environmental Characteristics ........................................................................53
5.5. Test Sequences ..............................................................................................54
5.5.1. Group 1: Mated Environmental....................................................................54
5.5.2. Group II: Mated Mechanical ........................................................................55
5.5.3. Group III: Mechanical Mate/Unmate Forces................................................56
5.5.4. Group IV: Insulator Integrity.........................................................................57
5.5.5. Group V: Cable Flexing ...............................................................................58
5.5.6. Group VI: Electrostatic Discharge ...............................................................58
Appendix A. Glossary of Terms ............................................................................59
Appendix B. Contact Geometry ........................................................................61
Appendix C. Digital Monitor Power State - State Diagram..............................76
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1. Introduction
The Digital Visual Interface (hereinafter DVI) specification provides a high-speed digital
connection for visual data types that is display technology independent. The interface is
primarily focused at providing a connection between a computer and its display device. The
DVI specification meets the needs of all segments of the PC industry (workstation, desktop,
laptop, etc) and will enable these different segments to unite around one monitor interface
specification.
The DVI interface enables:
1. Content to remain in the lossless digital domain from creation to consumption
2. Display technology independence
3. Plug and play through hot plug detection, EDID and DDC2B
4. Digital and Analog support in a single connector
This interface specification is organized as follows:
♦
Chapter 1 provides motivation, scope, and direction of the specification.
♦
Chapter 2 provides a technical overview and the specific system and display architectural
and programming requirements that must be met in order to create an inter-operable
context for the DVI interface.
♦
Chapter 3 provides a detailed description of the transition minimized differential
signaling (hereinafter T.M.D.S.) protocol and encoding algorithm.
♦
Chapter 4 provides a detailed description of the electrical requirements of T.M.D.S..
♦
Chapter 5 contains the connector mechanical description and the electrical characteristics
of the connector, including signal placement.
♦
Appendix A is a glossary.
♦
Appendix B details the connector contact geometry
♦
Appendix C enlarged digital monitor power state diagram
1.1. Scope and Motivation
The purpose of this interface specification is to provide an industry specification for a digital
interface between a personal computing device and a display device. This specification
provides for a simple low-cost implementation on both the host and monitor while allowing
for monitor manufacturers and system providers to add feature rich values as appropriate for
their specific application.
The DDWG has worked to address the various business models and requirements of the
industry by delivering a transition methodology that addresses the needs of those various
requirements. This is accomplished by specifying two connectors with identical mechanical
characteristics: one that is digital only and one that is digital and analog. The combined
digital and analog connector is designed to meet the needs of systems with special form factor
or performance requirements. Having support for the analog and digital interfaces for the
computer to monitor interconnect will allow the end user to simply plug the display into the
DVI connector regardless of the display technology.
The digital only DVI connector is designed to coexist with the standard VGA connector.
With the combined connector or the digital only connector the opportunity exists for the
removal of the legacy VGA connector. The removal of the legacy VGA connector is
anticipated to be driven strictly by business demands.
A digital interface for the computer to monitor interconnect has several benefits over the
standard VGA connector. A digital interface ensures all content transferred over this interface
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